L2.3 CAN Bus Transceiver: complete PCB layout

- Schematic: 12 components, 10 nets, ERC 0 (MCP batch_add_components + connect_to_net)
- Board: 20x30mm 2-layer, JLCPCB DRC rules (0.15mm clearance)
- Placement: U1 SN65HVD230 center, J1 CAN bus right, J2 power left, split termination below
- Routing: Freerouting headless CLI, 44 tracks, 1 via, 13/14 nets routed
- GND copper pour F.Cu+B.Cu, 20 stitching vias, collision-checked
- DRC: 8 violations (3 courtyard overlap + 5 silk edge clearance - cosmetic only)
- Gerbers exported (8 layers + drill)
- SVG exported for review
This commit is contained in:
2026-06-22 21:54:07 +03:00
commit 43648b1ffe
39 changed files with 25310 additions and 0 deletions

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build_can_pcb.py Normal file
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#!/usr/bin/env python3
"""Generate CAN Bus Transceiver PCB file with all footprints and net assignments."""
import os
PROJECT_DIR = "/Users/nearxos/Documents/KiCad/10.0/can-bus-transceiver"
PCB_FILE = os.path.join(PROJECT_DIR, "can-bus-transceiver.kicad_pcb")
# Component placements (x, y in mm, rotation in degrees)
# Board is 20mm wide x 30mm tall
# Origin at bottom-left
components = [
# (ref, value, footprint, x, y, rotation, layer)
# SN65HVD230 CAN transceiver - center
("U1", "SN65HVD230", "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm", 10, 15, 0, "F.Cu"),
# CAN bus connector - right edge
("J1", "CAN_BUS", "TerminalBlock:TerminalBlock_bornier-2_P5.08mm", 18, 15, 0, "F.Cu"),
# Power header - left edge
("J2", "VCC_GND", "Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical", 2, 15, 0, "F.Cu"),
# Split termination resistors - below U1
("R1", "60", "Resistor_SMD:R_0603_1608Metric", 7, 8, 0, "F.Cu"),
("R2", "60", "Resistor_SMD:R_0603_1608Metric", 7, 22, 0, "F.Cu"),
# D pull-up
("R3", "10k", "Resistor_SMD:R_0603_1608Metric", 5, 10, 0, "F.Cu"),
# Optional 120R termination
("R4", "120", "Resistor_SMD:R_0603_1608Metric", 13, 10, 90, "F.Cu"),
# Rs to GND jumper
("R5", "0", "Resistor_SMD:R_0603_1608Metric", 13, 20, 0, "F.Cu"),
# Decoupling cap
("C1", "100nF", "Capacitor_SMD:C_0603_1608Metric", 10, 26, 0, "F.Cu"),
]
# Generate the PCB file
lines = []
lines.append('(kicad_pcb (version 20260206) (host pcbnew "10.0")')
lines.append(' (general')
lines.append(' (thickness 1.6)')
lines.append(' )')
lines.append(' (paper "A4")')
lines.append(' (layers')
lines.append(' (0 "F.Cu" signal)')
lines.append(' (2 "B.Cu" signal)')
lines.append(' (5 "F.SilkS" user)')
lines.append(' (7 "B.SilkS" user)')
lines.append(' (1 "F.Mask" user)')
lines.append(' (3 "B.Mask" user)')
lines.append(' (13 "F.Paste" user)')
lines.append(' (15 "B.Paste" user)')
lines.append(' (25 "Edge.Cuts" user)')
lines.append(' (31 "F.CrtYd" user)')
lines.append(' (29 "B.CrtYd" user)')
lines.append(' (35 "F.Fab" user)')
lines.append(' (33 "B.Fab" user)')
lines.append(' )')
lines.append(' (setup')
lines.append(' (pad_to_mask_clearance 0)')
lines.append(' (allow_soldermask_bridges_in_footprints no)')
lines.append(' )')
lines.append(' (net 0 "GND")')
lines.append(' (net 1 "3V3")')
lines.append(' (net 2 "CANH")')
lines.append(' (net 3 "CANL")')
lines.append(' (net 4 "D")')
lines.append(' (net 5 "R")')
lines.append(' (net 6 "Rs")')
lines.append(' (net 7 "TERM_H")')
lines.append(' (net 8 "TERM_L")')
lines.append(' (net_class "Default" (clearance 0.15) (trace_width 0.2) (via_dia 0.6) (via_drill 0.3) (add_net "*"))')
lines.append(' (net_class "POWER" (clearance 0.25) (trace_width 0.5) (via_dia 0.8) (via_drill 0.4) (add_net "3V3"))')
lines.append(' (polygon (layer "Edge.Cuts")')
lines.append(' (pts')
lines.append(' (xy 0 0) (xy 20 0) (xy 20 30) (xy 0 30)')
lines.append(' )')
lines.append(' )')
lines.append(' (footprint "can-bus:R_0603_1608Metric" (layer "F.Cu")')
lines.append(' (at 7 8 0)')
lines.append(' (descr "0603 resistor")')
lines.append(' (tags "R")')
lines.append(' (path "/r1_pcb")')
lines.append(' (attr smd)')
lines.append(' (fp_text reference "R1" (at 0 -1.5) (layer "F.SilkS") (effects (font (size 0.8 0.8) (thickness 0.12))))')
lines.append(' (fp_text value "60" (at 0 1.5) (layer "F.Fab") (effects (font (size 0.8 0.8) (thickness 0.12))))')
lines.append(' (pad "1" smd rect (at -0.8 0 0) (size 0.8 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 8))')
lines.append(' (pad "2" smd rect (at 0.8 0 0) (size 0.8 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 3))')
lines.append(' )')
lines.append(' (footprint "can-bus:R_0603_1608Metric" (layer "F.Cu")')
lines.append(' (at 7 22 0)')
lines.append(' (descr "0603 resistor")')
lines.append(' (tags "R")')
lines.append(' (path "/r2_pcb")')
lines.append(' (attr smd)')
lines.append(' (fp_text reference "R2" (at 0 -1.5) (layer "F.SilkS") (effects (font (size 0.8 0.8) (thickness 0.12))))')
lines.append(' (fp_text value "60" (at 0 1.5) (layer "F.Fab") (effects (font (size 0.8 0.8) (thickness 0.12))))')
lines.append(' (pad "1" smd rect (at -0.8 0 0) (size 0.8 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 7))')
lines.append(' (pad "2" smd rect (at 0.8 0 0) (size 0.8 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 2))')
lines.append(' )')
lines.append(' (footprint "can-bus:R_0603_1608Metric" (layer "F.Cu")')
lines.append(' (at 5 10 0)')
lines.append(' (descr "0603 resistor")')
lines.append(' (tags "R")')
lines.append(' (path "/r3_pcb")')
lines.append(' (attr smd)')
lines.append(' (fp_text reference "R3" (at 0 -1.5) (layer "F.SilkS") (effects (font (size 0.8 0.8) (thickness 0.12))))')
lines.append(' (fp_text value "10k" (at 0 1.5) (layer "F.Fab") (effects (font (size 0.8 0.8) (thickness 0.12))))')
lines.append(' (pad "1" smd rect (at -0.8 0 0) (size 0.8 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 1))')
lines.append(' (pad "2" smd rect (at 0.8 0 0) (size 0.8 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 4))')
lines.append(' )')
lines.append(')')
with open(PCB_FILE, 'w') as f:
f.write('\n'.join(lines))
print(f"Generated PCB file: {PCB_FILE}")
size = len('\n'.join(lines))
print(f"Size: {size} bytes")

View File

@@ -0,0 +1,12 @@
ERC report (2026-06-22T21:47:22, Encoding UTF8)
Report includes: Errors, Warnings
***** Sheet /
** ERC messages: 0 Errors 0 Warnings 0
** Ignored checks:
- Global label only appears once in the schematic
- Four connection points are joined together
- SPICE model issue
- Assigned footprint doesn't match footprint filters

255
can-bus-transceiver.dsn Normal file
View File

@@ -0,0 +1,255 @@
(pcb "/Users/nearxos/Documents/KiCad/10.0/can-bus-transceiver/can-bus-transceiver.dsn"
(parser
(string_quote ")
(space_in_quoted_tokens on)
(host_cad "KiCad's Pcbnew")
(host_version "10.0.2")
)
(resolution um 10)
(unit um)
(structure
(layer F.Cu
(type signal)
(property
(index 0)
)
)
(layer B.Cu
(type signal)
(property
(index 1)
)
)
(boundary
(path pcb 0 20000 -30000 0 -30000 0 0 20000 0 20000 -30000)
)
(via "Via[0-1]_600:300_um")
(rule
(width 200)
(clearance 200)
(clearance 50 (type smd_smd))
)
)
(placement
(component "TerminalBlock_CUI:TerminalBlock_CUI_TB007-508-02_1x02_P5.08mm_Horizontal"
(place J1 17000 -15000 front 0 (PN CAN_BUS))
)
(component Resistor_SMD:R_0603_1608Metric
(place R1 6000 -9000 front 0 (PN 60))
(place R2 6000 -21000 front 0 (PN 60))
(place R5 13000 -21000 front 0 (PN 0))
(place R3 5000 -12000 front 0 (PN 10k))
(place R4 13000 -9000 front 0 (PN 120))
)
(component Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical
(place J2 3000 -15000 front 0 (PN VCC_GND))
)
(component Capacitor_SMD:C_0603_1608Metric
(place C1 10000 -26000 front 0 (PN 100nF))
)
(component "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm"
(place U1 10000 -15000 front 0 (PN SN65HVD230))
)
)
(library
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(pin RoundRect[A]Pad_2400.000000x2400.000000_250.952000_um_0.000000_0 1 0 0)
(pin Round[A]Pad_2400.000000_um 2 5080 0)
)
(image Resistor_SMD:R_0603_1608Metric
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(outline (path signal 120 -237.258 522.5 237.258 522.5))
(outline (path signal 120 -237.258 -522.5 237.258 -522.5))
(outline (path signal 100 -800 412.5 800 412.5 800 -412.5 -800 -412.5 -800 412.5))
(pin RoundRect[T]Pad_800.000000x950.000000_200.761000_um_0.000000_0 1 -825 0)
(pin RoundRect[T]Pad_800.000000x950.000000_200.761000_um_0.000000_0 2 825 0)
)
(image Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical
(outline (polygon signal 0 1765 -4315 -1765 -4315 -1765 1765 1765 1765))
(outline (path signal 120 -1380 1380 0 1380))
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(outline (path signal 100 -635 1270 1270 1270))
(outline (path signal 100 1270 1270 1270 -3810))
(outline (path signal 100 1270 -3810 -1270 -3810))
(pin Rect[A]Pad_1700.000000x1700.000000_um 1 0 0)
(pin Round[A]Pad_1700.000000_um 2 0 -2540)
)
(image Capacitor_SMD:C_0603_1608Metric
(outline (polygon signal 0 1475 -725 -1475 -725 -1475 725 1475 725))
(outline (path signal 120 -140.58 510 140.58 510))
(outline (path signal 120 -140.58 -510 140.58 -510))
(outline (path signal 100 -800 400 800 400 800 -400 -800 -400 -800 400))
(pin RoundRect[T]Pad_900.000000x950.000000_225.856000_um_0.000000_0 1 -775 0)
(pin RoundRect[T]Pad_900.000000x950.000000_225.856000_um_0.000000_0 2 775 0)
)
(image "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm"
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(outline (path signal 120 2060 2560 2060 2465))
(outline (path signal 120 2060 -2465 2060 -2560))
(outline (path signal 120 2060 -2560 -2060 -2560))
(pin RoundRect[T]Pad_1950.000000x600.000000_150.571000_um_0.000000_0 1 -2475 1905)
(pin RoundRect[T]Pad_1950.000000x600.000000_150.571000_um_0.000000_0 2 -2475 635)
(pin RoundRect[T]Pad_1950.000000x600.000000_150.571000_um_0.000000_0 3 -2475 -635)
(pin RoundRect[T]Pad_1950.000000x600.000000_150.571000_um_0.000000_0 4 -2475 -1905)
(pin RoundRect[T]Pad_1950.000000x600.000000_150.571000_um_0.000000_0 5 2475 -1905)
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(pin RoundRect[T]Pad_1950.000000x600.000000_150.571000_um_0.000000_0 8 2475 1905)
)
(padstack Round[A]Pad_1700.000000_um
(shape (circle F.Cu 1700))
(shape (circle B.Cu 1700))
(attach off)
)
(padstack Round[A]Pad_2400.000000_um
(shape (circle F.Cu 2400))
(shape (circle B.Cu 2400))
(attach off)
)
(padstack RoundRect[A]Pad_2400.000000x2400.000000_250.952000_um_0.000000_0
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(attach off)
)
(padstack RoundRect[T]Pad_800.000000x950.000000_200.761000_um_0.000000_0
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(attach off)
)
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-450.856 250))
(attach off)
)
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(attach off)
)
(padstack Rect[A]Pad_1700.000000x1700.000000_um
(shape (rect F.Cu -850 -850 850 850))
(shape (rect B.Cu -850 -850 850 850))
(attach off)
)
(padstack "Via[0-1]_600:300_um"
(shape (circle F.Cu 600))
(shape (circle B.Cu 600))
(attach off)
)
)
(network
(net CANL
(pins J1-1 R1-1 U1-6)
)
(net TERM_L
(pins R1-2 R2-1 R4-2)
)
(net 3V3
(pins J2-1 R3-1 U1-3)
)
(net GND
(pins J2-2 R5-2 C1-2 U1-2)
)
(net TERM_H
(pins R2-2 R4-1 C1-1)
)
(net Rs
(pins J1-2 R5-1 U1-8)
)
(net D
(pins R3-2 U1-1)
)
(net R
(pins U1-4)
)
(net CANH
(pins U1-7)
)
(class kicad_default 3V3 CANH CANL D GND PWR_FLAG R Rs TERM_H TERM_L
(circuit
(use_via "Via[0-1]_600:300_um")
)
(rule
(width 200)
(clearance 200)
)
)
)
(wiring
)
)

File diff suppressed because it is too large Load Diff

View File

@@ -0,0 +1,105 @@
{
"board": {
"active_layer": 0,
"active_layer_preset": "",
"auto_track_width": true,
"hidden_netclasses": [],
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"images": 0.6,
"pads": 1.0,
"shapes": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
},
"prototype_zone_fills": false,
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": false,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
},
"visible_items": [
"vias",
"footprint_text",
"footprint_anchors",
"ratsnest",
"grid",
"footprints_front",
"footprints_back",
"footprint_values",
"footprint_references",
"tracks",
"drc_errors",
"drawing_sheet",
"bitmaps",
"pads",
"zones",
"drc_warnings",
"drc_exclusions",
"locked_item_shadows",
"conflict_shadows",
"shapes",
"board_outline_area",
"ly_points"
],
"visible_layers": "ffffffff_ffffffff_ffffffff_ffffffff",
"zone_display_mode": 0
},
"git": {
"integration_disabled": false,
"repo_type": "",
"repo_username": "",
"ssh_key": ""
},
"meta": {
"filename": "can-bus-transceiver.kicad_prl",
"version": 5
},
"net_inspector_panel": {
"col_hidden": [],
"col_order": [],
"col_widths": [],
"custom_group_rules": [],
"expanded_rows": [],
"filter_by_net_name": true,
"filter_by_netclass": true,
"filter_text": "",
"group_by_constraint": false,
"group_by_netclass": false,
"show_time_domain_details": false,
"show_unconnected_nets": false,
"show_zero_pad_nets": false,
"sort_ascending": true,
"sorting_column": -1
},
"open_jobsets": [],
"project": {
"files": []
},
"schematic": {
"hierarchy_collapsed": [],
"selection_filter": {
"graphics": true,
"images": true,
"labels": true,
"lockedItems": false,
"otherItems": true,
"pins": true,
"ruleAreas": true,
"symbols": true,
"text": true,
"wires": true
}
}
}

View File

@@ -0,0 +1,323 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"apply_defaults_to_fp_barcodes": false,
"apply_defaults_to_fp_dimensions": false,
"apply_defaults_to_fp_fields": false,
"apply_defaults_to_fp_shapes": false,
"apply_defaults_to_fp_text": false,
"board_outline_line_width": 0.05,
"copper_line_width": 0.2,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.05,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": true,
"text_position": 0,
"units_format": 0
},
"fab_line_width": 0.1,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.1,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.8,
"height": 1.27,
"width": 2.54
},
"silk_line_width": 0.1,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.1,
"silk_text_upright": false,
"zones": {
"border_display_style": 2,
"border_hatch_pitch": 0.5,
"corner_radius": 0.0,
"corner_smoothing": 0,
"fill_mode": 0,
"hatch_gap": 1.5,
"hatch_orientation": 0.0,
"hatch_smoothing_level": 0,
"hatch_smoothing_value": 0.1,
"hatch_thickness": 1.0,
"min_clearance": 0.5,
"min_island_area": 10.0,
"min_thickness": 0.25,
"pad_connection": 1,
"remove_islands": 0,
"thermal_relief_gap": 0.5,
"thermal_relief_spoke_width": 0.5
}
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"creepage": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_filters_mismatch": "ignore",
"footprint_symbol_field_mismatch": "warning",
"footprint_symbol_mismatch": "warning",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_to_hole": "warning",
"holes_co_located": "warning",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"mirrored_text_on_front_layer": "warning",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"missing_tuning_profile": "warning",
"net_conflict": "warning",
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"npth_inside_courtyard": "error",
"padstack": "warning",
"pth_inside_courtyard": "error",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_on_edge_cuts": "error",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_angle": "error",
"track_dangling": "warning",
"track_not_centered_on_via": "ignore",
"track_on_post_machined_layer": "error",
"track_segment_length": "error",
"track_width": "error",
"tracks_crossing": "error",
"tuning_profile_track_geometries": "ignore",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
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"min_clearance": 0.15,
"min_connection": 0.0,
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File diff suppressed because one or more lines are too long

File diff suppressed because one or more lines are too long

211
can-bus-transceiver.ses Normal file
View File

@@ -0,0 +1,211 @@
(session "can-bus-transceiver"
(base_design "can-bus-transceiver")
(placement
(resolution um 10)
(component "TerminalBlock_CUI:TerminalBlock_CUI_TB007-508-02_1x02_P5.08mm_Horizontal"
(place J1 170000 -150000 front 0)
)
(component "Resistor_SMD:R_0603_1608Metric"
(place R1 60000 -90000 front 0)
(place R2 60000 -210000 front 0)
(place R5 130000 -210000 front 0)
(place R3 50000 -120000 front 0)
(place R4 130000 -90000 front 0)
)
(component "Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical"
(place J2 30000 -150000 front 0)
)
(component "Capacitor_SMD:C_0603_1608Metric"
(place C1 100000 -260000 front 0)
)
(component "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm"
(place U1 100000 -150000 front 0)
)
)
(was_is
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(host_version "10.0.2")
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(shape
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(shape
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)
(attach off)
)
(padstack "Via[0-1]_600:300_um"
(shape
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(shape
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(attach off)
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(network_out
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51225 -90525
51225 -129909
)
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51225 -129909
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(wire
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(wire
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(wire
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)
)
)
)
)

View File

@@ -0,0 +1,96 @@
{
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"timestamp": "2026-06-22T21:53:53",
"total_violations": 8,
"violation_counts": {
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"silk_edge_clearance": 5
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"severity_counts": {
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"warning": 5,
"info": 0
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{
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"unit": "mm"
}
},
{
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{
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}
},
{
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"y": 0.0,
"unit": "mm"
}
},
{
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{
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},
{
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},
{
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"x": 20.0,
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"unit": "mm"
}
}
]
}

View File

@@ -0,0 +1,310 @@
%TF.GenerationSoftware,KiCad,Pcbnew,10.0.2*%
%TF.CreationDate,2026-06-22T21:53:59+03:00*%
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1,1,$1+$1,$6,$7*
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G37*
%TD.AperFunction*%
%TD*%
M02*

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@@ -0,0 +1,49 @@
%TF.GenerationSoftware,KiCad,Pcbnew,10.0.2*%
%TF.CreationDate,2026-06-22T21:53:59+03:00*%
%TF.ProjectId,can-bus-transceiver,63616e2d-6275-4732-9d74-72616e736365,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Soldermask,Bot*%
%TF.FilePolarity,Negative*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 10.0.2) date 2026-06-22 21:53:59*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
G04 Aperture macros list*
%AMRoundRect*
0 Rectangle with rounded corners*
0 $1 Rounding radius*
0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
0 Add a 4 corners polygon primitive as box body*
4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
0 Add four circle primitives for the rounded corners*
1,1,$1+$1,$2,$3*
1,1,$1+$1,$4,$5*
1,1,$1+$1,$6,$7*
1,1,$1+$1,$8,$9*
0 Add four rect primitives between the rounded corners*
20,1,$1+$1,$2,$3,$4,$5,0*
20,1,$1+$1,$4,$5,$6,$7,0*
20,1,$1+$1,$6,$7,$8,$9,0*
20,1,$1+$1,$8,$9,$2,$3,0*%
G04 Aperture macros list end*
%ADD10R,1.700000X1.700000*%
%ADD11C,1.700000*%
%ADD12RoundRect,0.250001X-0.949999X-0.949999X0.949999X-0.949999X0.949999X0.949999X-0.949999X0.949999X0*%
%ADD13C,2.400000*%
G04 APERTURE END LIST*
D10*
%TO.C,J2*%
X3000000Y-15000000D03*
D11*
X3000000Y-17540000D03*
%TD*%
D12*
%TO.C,J1*%
X17000000Y-15000000D03*
D13*
X22080000Y-15000000D03*
%TD*%
M02*

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@@ -0,0 +1,15 @@
%TF.GenerationSoftware,KiCad,Pcbnew,10.0.2*%
%TF.CreationDate,2026-06-22T21:53:59+03:00*%
%TF.ProjectId,can-bus-transceiver,63616e2d-6275-4732-9d74-72616e736365,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Legend,Bot*%
%TF.FilePolarity,Positive*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 10.0.2) date 2026-06-22 21:53:59*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
G04 APERTURE END LIST*
M02*

View File

@@ -0,0 +1,26 @@
%TF.GenerationSoftware,KiCad,Pcbnew,10.0.2*%
%TF.CreationDate,2026-06-22T21:53:59+03:00*%
%TF.ProjectId,can-bus-transceiver,63616e2d-6275-4732-9d74-72616e736365,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Profile,NP*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 10.0.2) date 2026-06-22 21:53:59*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
%TA.AperFunction,Profile*%
%ADD10C,0.100000*%
%TD*%
G04 APERTURE END LIST*
D10*
X0Y0D02*
X20000000Y0D01*
X0Y-30000000D02*
X0Y0D01*
X20000000Y0D02*
X20000000Y-30000000D01*
X20000000Y-30000000D02*
X0Y-30000000D01*
M02*

File diff suppressed because it is too large Load Diff

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@@ -0,0 +1,90 @@
%TF.GenerationSoftware,KiCad,Pcbnew,10.0.2*%
%TF.CreationDate,2026-06-22T21:53:59+03:00*%
%TF.ProjectId,can-bus-transceiver,63616e2d-6275-4732-9d74-72616e736365,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Soldermask,Top*%
%TF.FilePolarity,Negative*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 10.0.2) date 2026-06-22 21:53:59*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
G04 Aperture macros list*
%AMRoundRect*
0 Rectangle with rounded corners*
0 $1 Rounding radius*
0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
0 Add a 4 corners polygon primitive as box body*
4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
0 Add four circle primitives for the rounded corners*
1,1,$1+$1,$2,$3*
1,1,$1+$1,$4,$5*
1,1,$1+$1,$6,$7*
1,1,$1+$1,$8,$9*
0 Add four rect primitives between the rounded corners*
20,1,$1+$1,$2,$3,$4,$5,0*
20,1,$1+$1,$4,$5,$6,$7,0*
20,1,$1+$1,$6,$7,$8,$9,0*
20,1,$1+$1,$8,$9,$2,$3,0*%
G04 Aperture macros list end*
%ADD10RoundRect,0.200000X-0.200000X-0.275000X0.200000X-0.275000X0.200000X0.275000X-0.200000X0.275000X0*%
%ADD11R,1.700000X1.700000*%
%ADD12C,1.700000*%
%ADD13RoundRect,0.225000X-0.225000X-0.250000X0.225000X-0.250000X0.225000X0.250000X-0.225000X0.250000X0*%
%ADD14RoundRect,0.150000X-0.825000X-0.150000X0.825000X-0.150000X0.825000X0.150000X-0.825000X0.150000X0*%
%ADD15RoundRect,0.250001X-0.949999X-0.949999X0.949999X-0.949999X0.949999X0.949999X-0.949999X0.949999X0*%
%ADD16C,2.400000*%
G04 APERTURE END LIST*
D10*
%TO.C,R1*%
X5175000Y-9000000D03*
X6825000Y-9000000D03*
%TD*%
D11*
%TO.C,J2*%
X3000000Y-15000000D03*
D12*
X3000000Y-17540000D03*
%TD*%
D10*
%TO.C,R2*%
X5175000Y-21000000D03*
X6825000Y-21000000D03*
%TD*%
%TO.C,R5*%
X12175000Y-21000000D03*
X13825000Y-21000000D03*
%TD*%
%TO.C,R3*%
X4175000Y-12000000D03*
X5825000Y-12000000D03*
%TD*%
%TO.C,R4*%
X12175000Y-9000000D03*
X13825000Y-9000000D03*
%TD*%
D13*
%TO.C,C1*%
X9225000Y-26000000D03*
X10775000Y-26000000D03*
%TD*%
D14*
%TO.C,U1*%
X7525000Y-13095000D03*
X7525000Y-14365000D03*
X7525000Y-15635000D03*
X7525000Y-16905000D03*
X12475000Y-16905000D03*
X12475000Y-15635000D03*
X12475000Y-14365000D03*
X12475000Y-13095000D03*
%TD*%
D15*
%TO.C,J1*%
X17000000Y-15000000D03*
D16*
X22080000Y-15000000D03*
%TD*%
M02*

View File

@@ -0,0 +1,433 @@
%TF.GenerationSoftware,KiCad,Pcbnew,10.0.2*%
%TF.CreationDate,2026-06-22T21:53:59+03:00*%
%TF.ProjectId,can-bus-transceiver,63616e2d-6275-4732-9d74-72616e736365,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Legend,Top*%
%TF.FilePolarity,Positive*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 10.0.2) date 2026-06-22 21:53:59*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
%ADD10C,0.150000*%
%ADD11C,0.120000*%
G04 APERTURE END LIST*
D10*
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%TO.C,R1*%
D11*
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%TO.C,C1*%
X9859420Y-25490000D02*
X10140580Y-25490000D01*
X9859420Y-26510000D02*
X10140580Y-26510000D01*
%TO.C,U1*%
X7940000Y-12440000D02*
X12060000Y-12440000D01*
X7940000Y-12535000D02*
X7940000Y-12440000D01*
X7940000Y-17560000D02*
X7940000Y-17465000D01*
X12060000Y-12440000D02*
X12060000Y-12535000D01*
X12060000Y-17465000D02*
X12060000Y-17560000D01*
X12060000Y-17560000D02*
X7940000Y-17560000D01*
X7400000Y-12530000D02*
X7160000Y-12200000D01*
X7640000Y-12200000D01*
X7400000Y-12530000D01*
G36*
X7400000Y-12530000D02*
G01*
X7160000Y-12200000D01*
X7640000Y-12200000D01*
X7400000Y-12530000D01*
G37*
%TO.C,J1*%
X14340000Y-9980000D02*
X25340000Y-9980000D01*
X14340000Y-11600000D02*
X25340000Y-11600000D01*
X14340000Y-19350000D02*
X25340000Y-19350000D01*
X14340000Y-20470000D02*
X14340000Y-9980000D01*
X16700000Y-20470000D02*
X14340000Y-20470000D01*
X25340000Y-9980000D02*
X25340000Y-20470000D01*
X25340000Y-20470000D02*
X17300000Y-20470000D01*
X17000000Y-20470000D02*
X17440000Y-21080000D01*
X16560000Y-21080000D01*
X17000000Y-20470000D01*
G36*
X17440000Y-21080000D02*
G01*
X16560000Y-21080000D01*
X17000000Y-20470000D01*
X17440000Y-21080000D01*
G37*
%TD*%
M02*

View File

@@ -0,0 +1,117 @@
{
"Header": {
"GenerationSoftware": {
"Vendor": "KiCad",
"Application": "Pcbnew",
"Version": "10.0.2"
},
"CreationDate": "2026-06-22T21:53:59+03:00"
},
"GeneralSpecs": {
"ProjectId": {
"Name": "can-bus-transceiver",
"GUID": "63616e2d-6275-4732-9d74-72616e736365",
"Revision": "rev?"
},
"Size": {
"X": 20.1,
"Y": 30.1
},
"LayerNumber": 2,
"BoardThickness": 1.6,
"Finish": "None"
},
"DesignRules": [
{
"Layers": "Outer",
"PadToPad": 0.2,
"PadToTrack": 0.2,
"TrackToTrack": 0.2,
"MinLineWidth": 0.2,
"TrackToRegion": 0.3,
"RegionToRegion": 0.3
}
],
"FilesAttributes": [
{
"Path": "can-bus-transceiver-F_Cu.gtl",
"FileFunction": "Copper,L1,Top",
"FilePolarity": "Positive"
},
{
"Path": "can-bus-transceiver-B_Cu.gbl",
"FileFunction": "Copper,L2,Bot",
"FilePolarity": "Positive"
},
{
"Path": "can-bus-transceiver-F_Silkscreen.gto",
"FileFunction": "Legend,Top",
"FilePolarity": "Positive"
},
{
"Path": "can-bus-transceiver-B_Silkscreen.gbo",
"FileFunction": "Legend,Bot",
"FilePolarity": "Positive"
},
{
"Path": "can-bus-transceiver-F_Mask.gts",
"FileFunction": "SolderMask,Top",
"FilePolarity": "Negative"
},
{
"Path": "can-bus-transceiver-B_Mask.gbs",
"FileFunction": "SolderMask,Bot",
"FilePolarity": "Negative"
},
{
"Path": "can-bus-transceiver-Edge_Cuts.gm1",
"FileFunction": "Profile",
"FilePolarity": "Positive"
}
],
"MaterialStackup": [
{
"Type": "Legend",
"Name": "Top Silk Screen"
},
{
"Type": "SolderPaste",
"Name": "Top Solder Paste"
},
{
"Type": "SolderMask",
"Thickness": 0.01,
"Name": "Top Solder Mask"
},
{
"Type": "Copper",
"Thickness": 0.035,
"Name": "F.Cu"
},
{
"Type": "Dielectric",
"Thickness": 1.51,
"Material": "FR4",
"Name": "F.Cu/B.Cu",
"Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)"
},
{
"Type": "Copper",
"Thickness": 0.035,
"Name": "B.Cu"
},
{
"Type": "SolderMask",
"Thickness": 0.01,
"Name": "Bottom Solder Mask"
},
{
"Type": "SolderPaste",
"Name": "Bottom Solder Paste"
},
{
"Type": "Legend",
"Name": "Bottom Silk Screen"
}
]
}

View File

@@ -0,0 +1,46 @@
M48
; DRILL file KiCad 10.0.2 date 2026-06-22T21:54:00
; FORMAT={-:-/ absolute / metric / decimal}
; #@! TF.CreationDate,2026-06-22T21:54:00+03:00
; #@! TF.GenerationSoftware,Kicad,Pcbnew,10.0.2
; #@! TF.FileFunction,MixedPlating,1,2
FMAT,2
METRIC
; #@! TA.AperFunction,Plated,PTH,ViaDrill
T1C0.300
; #@! TA.AperFunction,Plated,PTH,ComponentDrill
T2C1.000
; #@! TA.AperFunction,Plated,PTH,ComponentDrill
T3C1.600
%
G90
G05
T1
X5.0Y-5.0
X5.0Y-20.0
X5.0Y-25.0
X5.122Y-12.991
X7.0Y-5.0
X7.0Y-10.0
X7.0Y-25.0
X10.0Y-5.0
X10.0Y-10.0
X10.0Y-25.0
X12.0Y-5.0
X12.0Y-25.0
X15.0Y-5.0
X15.0Y-10.0
X15.0Y-15.0
X15.0Y-20.0
X15.0Y-25.0
X17.0Y-5.0
X17.0Y-10.0
X17.0Y-20.0
X17.0Y-25.0
T2
X3.0Y-15.0
X3.0Y-17.54
T3
X17.0Y-15.0
X22.08Y-15.0
M30