nearxos
43648b1ffe
- Schematic: 12 components, 10 nets, ERC 0 (MCP batch_add_components + connect_to_net) - Board: 20x30mm 2-layer, JLCPCB DRC rules (0.15mm clearance) - Placement: U1 SN65HVD230 center, J1 CAN bus right, J2 power left, split termination below - Routing: Freerouting headless CLI, 44 tracks, 1 via, 13/14 nets routed - GND copper pour F.Cu+B.Cu, 20 stitching vias, collision-checked - DRC: 8 violations (3 courtyard overlap + 5 silk edge clearance - cosmetic only) - Gerbers exported (8 layers + drill) - SVG exported for review
117 lines
5.3 KiB
Python
117 lines
5.3 KiB
Python
#!/usr/bin/env python3
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"""Generate CAN Bus Transceiver PCB file with all footprints and net assignments."""
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import os
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PROJECT_DIR = "/Users/nearxos/Documents/KiCad/10.0/can-bus-transceiver"
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PCB_FILE = os.path.join(PROJECT_DIR, "can-bus-transceiver.kicad_pcb")
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# Component placements (x, y in mm, rotation in degrees)
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# Board is 20mm wide x 30mm tall
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# Origin at bottom-left
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components = [
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# (ref, value, footprint, x, y, rotation, layer)
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# SN65HVD230 CAN transceiver - center
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("U1", "SN65HVD230", "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm", 10, 15, 0, "F.Cu"),
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# CAN bus connector - right edge
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("J1", "CAN_BUS", "TerminalBlock:TerminalBlock_bornier-2_P5.08mm", 18, 15, 0, "F.Cu"),
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# Power header - left edge
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("J2", "VCC_GND", "Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical", 2, 15, 0, "F.Cu"),
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# Split termination resistors - below U1
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("R1", "60", "Resistor_SMD:R_0603_1608Metric", 7, 8, 0, "F.Cu"),
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("R2", "60", "Resistor_SMD:R_0603_1608Metric", 7, 22, 0, "F.Cu"),
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# D pull-up
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("R3", "10k", "Resistor_SMD:R_0603_1608Metric", 5, 10, 0, "F.Cu"),
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# Optional 120R termination
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("R4", "120", "Resistor_SMD:R_0603_1608Metric", 13, 10, 90, "F.Cu"),
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# Rs to GND jumper
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("R5", "0", "Resistor_SMD:R_0603_1608Metric", 13, 20, 0, "F.Cu"),
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# Decoupling cap
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("C1", "100nF", "Capacitor_SMD:C_0603_1608Metric", 10, 26, 0, "F.Cu"),
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]
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# Generate the PCB file
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lines = []
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lines.append('(kicad_pcb (version 20260206) (host pcbnew "10.0")')
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lines.append(' (general')
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lines.append(' (thickness 1.6)')
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lines.append(' )')
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lines.append(' (paper "A4")')
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lines.append(' (layers')
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lines.append(' (0 "F.Cu" signal)')
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lines.append(' (2 "B.Cu" signal)')
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lines.append(' (5 "F.SilkS" user)')
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lines.append(' (7 "B.SilkS" user)')
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lines.append(' (1 "F.Mask" user)')
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lines.append(' (3 "B.Mask" user)')
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lines.append(' (13 "F.Paste" user)')
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lines.append(' (15 "B.Paste" user)')
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lines.append(' (25 "Edge.Cuts" user)')
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lines.append(' (31 "F.CrtYd" user)')
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lines.append(' (29 "B.CrtYd" user)')
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lines.append(' (35 "F.Fab" user)')
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lines.append(' (33 "B.Fab" user)')
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lines.append(' )')
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lines.append(' (setup')
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lines.append(' (pad_to_mask_clearance 0)')
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lines.append(' (allow_soldermask_bridges_in_footprints no)')
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lines.append(' )')
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lines.append(' (net 0 "GND")')
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lines.append(' (net 1 "3V3")')
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lines.append(' (net 2 "CANH")')
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lines.append(' (net 3 "CANL")')
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lines.append(' (net 4 "D")')
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lines.append(' (net 5 "R")')
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lines.append(' (net 6 "Rs")')
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lines.append(' (net 7 "TERM_H")')
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lines.append(' (net 8 "TERM_L")')
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lines.append(' (net_class "Default" (clearance 0.15) (trace_width 0.2) (via_dia 0.6) (via_drill 0.3) (add_net "*"))')
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lines.append(' (net_class "POWER" (clearance 0.25) (trace_width 0.5) (via_dia 0.8) (via_drill 0.4) (add_net "3V3"))')
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lines.append(' (polygon (layer "Edge.Cuts")')
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lines.append(' (pts')
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lines.append(' (xy 0 0) (xy 20 0) (xy 20 30) (xy 0 30)')
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lines.append(' )')
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lines.append(' )')
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lines.append(' (footprint "can-bus:R_0603_1608Metric" (layer "F.Cu")')
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lines.append(' (at 7 8 0)')
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lines.append(' (descr "0603 resistor")')
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lines.append(' (tags "R")')
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lines.append(' (path "/r1_pcb")')
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lines.append(' (attr smd)')
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lines.append(' (fp_text reference "R1" (at 0 -1.5) (layer "F.SilkS") (effects (font (size 0.8 0.8) (thickness 0.12))))')
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lines.append(' (fp_text value "60" (at 0 1.5) (layer "F.Fab") (effects (font (size 0.8 0.8) (thickness 0.12))))')
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lines.append(' (pad "1" smd rect (at -0.8 0 0) (size 0.8 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 8))')
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lines.append(' (pad "2" smd rect (at 0.8 0 0) (size 0.8 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 3))')
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lines.append(' )')
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lines.append(' (footprint "can-bus:R_0603_1608Metric" (layer "F.Cu")')
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lines.append(' (at 7 22 0)')
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lines.append(' (descr "0603 resistor")')
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lines.append(' (tags "R")')
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lines.append(' (path "/r2_pcb")')
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lines.append(' (attr smd)')
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lines.append(' (fp_text reference "R2" (at 0 -1.5) (layer "F.SilkS") (effects (font (size 0.8 0.8) (thickness 0.12))))')
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lines.append(' (fp_text value "60" (at 0 1.5) (layer "F.Fab") (effects (font (size 0.8 0.8) (thickness 0.12))))')
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lines.append(' (pad "1" smd rect (at -0.8 0 0) (size 0.8 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 7))')
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lines.append(' (pad "2" smd rect (at 0.8 0 0) (size 0.8 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 2))')
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lines.append(' )')
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lines.append(' (footprint "can-bus:R_0603_1608Metric" (layer "F.Cu")')
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lines.append(' (at 5 10 0)')
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lines.append(' (descr "0603 resistor")')
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lines.append(' (tags "R")')
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lines.append(' (path "/r3_pcb")')
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lines.append(' (attr smd)')
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lines.append(' (fp_text reference "R3" (at 0 -1.5) (layer "F.SilkS") (effects (font (size 0.8 0.8) (thickness 0.12))))')
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lines.append(' (fp_text value "10k" (at 0 1.5) (layer "F.Fab") (effects (font (size 0.8 0.8) (thickness 0.12))))')
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lines.append(' (pad "1" smd rect (at -0.8 0 0) (size 0.8 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 1))')
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lines.append(' (pad "2" smd rect (at 0.8 0 0) (size 0.8 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 4))')
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lines.append(' )')
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lines.append(')')
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with open(PCB_FILE, 'w') as f:
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f.write('\n'.join(lines))
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print(f"Generated PCB file: {PCB_FILE}")
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size = len('\n'.join(lines))
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print(f"Size: {size} bytes")
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