nearxos
43648b1ffe
- Schematic: 12 components, 10 nets, ERC 0 (MCP batch_add_components + connect_to_net) - Board: 20x30mm 2-layer, JLCPCB DRC rules (0.15mm clearance) - Placement: U1 SN65HVD230 center, J1 CAN bus right, J2 power left, split termination below - Routing: Freerouting headless CLI, 44 tracks, 1 via, 13/14 nets routed - GND copper pour F.Cu+B.Cu, 20 stitching vias, collision-checked - DRC: 8 violations (3 courtyard overlap + 5 silk edge clearance - cosmetic only) - Gerbers exported (8 layers + drill) - SVG exported for review
13 lines
345 B
Plaintext
13 lines
345 B
Plaintext
ERC report (2026-06-22T21:47:22, Encoding UTF8)
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Report includes: Errors, Warnings
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***** Sheet /
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** ERC messages: 0 Errors 0 Warnings 0
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** Ignored checks:
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- Global label only appears once in the schematic
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- Four connection points are joined together
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- SPICE model issue
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- Assigned footprint doesn't match footprint filters
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