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43648b1ffefd1735626ada54c4dc18d9fcbbca22
can-bus-transceiver/can-bus-transceiver.dsn
nearxos 43648b1ffe L2.3 CAN Bus Transceiver: complete PCB layout 
- Schematic: 12 components, 10 nets, ERC 0 (MCP batch_add_components + connect_to_net)
- Board: 20x30mm 2-layer, JLCPCB DRC rules (0.15mm clearance)
- Placement: U1 SN65HVD230 center, J1 CAN bus right, J2 power left, split termination below
- Routing: Freerouting headless CLI, 44 tracks, 1 via, 13/14 nets routed
- GND copper pour F.Cu+B.Cu, 20 stitching vias, collision-checked
- DRC: 8 violations (3 courtyard overlap + 5 silk edge clearance - cosmetic only)
- Gerbers exported (8 layers + drill)
- SVG exported for review
2026-06-22 21:54:07 +03:00

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(pcb "/Users/nearxos/Documents/KiCad/10.0/can-bus-transceiver/can-bus-transceiver.dsn"
(parser
(string_quote ")
(space_in_quoted_tokens on)
(host_cad "KiCad's Pcbnew")
(host_version "10.0.2")
)
(resolution um 10)
(unit um)
(structure
(layer F.Cu
(type signal)
(property
(index 0)
)
)
(layer B.Cu
(type signal)
(property
(index 1)
)
)
(boundary
(path pcb 0 20000 -30000 0 -30000 0 0 20000 0 20000 -30000)
)
(via "Via[0-1]_600:300_um")
(rule
(width 200)
(clearance 200)
(clearance 50 (type smd_smd))
)
)
(placement
(component "TerminalBlock_CUI:TerminalBlock_CUI_TB007-508-02_1x02_P5.08mm_Horizontal"
(place J1 17000 -15000 front 0 (PN CAN_BUS))
)
(component Resistor_SMD:R_0603_1608Metric
(place R1 6000 -9000 front 0 (PN 60))
(place R2 6000 -21000 front 0 (PN 60))
(place R5 13000 -21000 front 0 (PN 0))
(place R3 5000 -12000 front 0 (PN 10k))
(place R4 13000 -9000 front 0 (PN 120))
)
(component Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical
(place J2 3000 -15000 front 0 (PN VCC_GND))
)
(component Capacitor_SMD:C_0603_1608Metric
(place C1 10000 -26000 front 0 (PN 100nF))
)
(component "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm"
(place U1 10000 -15000 front 0 (PN SN65HVD230))
)
)
(library
(image "TerminalBlock_CUI:TerminalBlock_CUI_TB007-508-02_1x02_P5.08mm_Horizontal"
(outline (polygon signal 0 8715 -5845 -3035 -5845 -3035 5395 8715 5395))
(outline (path signal 120 -2660 5020 8340 5020))
(outline (path signal 120 -2660 3400 8340 3400))
(outline (path signal 120 -2660 -4350 8340 -4350))
(outline (path signal 120 -2660 -5470 -2660 5020))
(outline (path signal 120 -300 -5470 -2660 -5470))
(outline (path signal 120 8340 5020 8340 -5470))
(outline (path signal 120 8340 -5470 300 -5470))
(outline (path signal 100 -2540 4900 8220 4900))
(outline (path signal 100 -2540 3400 8220 3400))
(outline (path signal 100 -2540 -4350 -2540 4900))
(outline (path signal 100 -2540 -4350 8220 -4350))
(outline (path signal 100 -1540 -5350 -2540 -4350))
(outline (path signal 100 1177 1403 -1403 -1177))
(outline (path signal 100 1403 1177 -1177 -1403))
(outline (path signal 100 6257 1403 3677 -1177))
(outline (path signal 100 6483 1177 3903 -1403))
(outline (path signal 100 8220 4900 8220 -5350))
(outline (path signal 100 8220 -5350 -1540 -5350))
(outline (path signal 100 1850 0 1831.17 -263.282 1775.06 -521.205 1682.82 -768.518
1556.32 -1000.19 1398.14 -1211.49 1211.49 -1398.14 1000.19 -1556.32
768.518 -1682.82 521.205 -1775.06 263.282 -1831.17 0 -1850
-263.282 -1831.17 -521.205 -1775.06 -768.518 -1682.82 -1000.19 -1556.32
-1211.49 -1398.14 -1398.14 -1211.49 -1556.32 -1000.19 -1682.82 -768.518
-1775.06 -521.205 -1831.17 -263.282 -1850 0 -1831.17 263.282
-1775.06 521.205 -1682.82 768.518 -1556.32 1000.19 -1398.14 1211.49
-1211.49 1398.14 -1000.19 1556.32 -768.518 1682.82 -521.205 1775.06
-263.282 1831.17 0 1850 263.282 1831.17 521.205 1775.06 768.518 1682.82
1000.19 1556.32 1211.49 1398.14 1398.14 1211.49 1556.32 1000.19
1682.82 768.518 1775.06 521.205 1831.17 263.282 1850 0))
(outline (path signal 100 6930 0 6911.17 -263.282 6855.06 -521.205 6762.82 -768.518
6636.32 -1000.19 6478.14 -1211.49 6291.49 -1398.14 6080.19 -1556.32
5848.52 -1682.82 5601.2 -1775.06 5343.28 -1831.17 5080 -1850
4816.72 -1831.17 4558.8 -1775.06 4311.48 -1682.82 4079.81 -1556.32
3868.51 -1398.14 3681.86 -1211.49 3523.68 -1000.19 3397.18 -768.518
3304.94 -521.205 3248.83 -263.282 3230 0 3248.83 263.282
3304.94 521.205 3397.18 768.518 3523.68 1000.19 3681.86 1211.49
3868.51 1398.14 4079.81 1556.32 4311.48 1682.82 4558.8 1775.06
4816.72 1831.17 5080 1850 5343.28 1831.17 5601.2 1775.06
5848.52 1682.82 6080.19 1556.32 6291.49 1398.14 6478.14 1211.49
6636.32 1000.19 6762.82 768.518 6855.06 521.205 6911.17 263.282
6930 0))
(pin RoundRect[A]Pad_2400.000000x2400.000000_250.952000_um_0.000000_0 1 0 0)
(pin Round[A]Pad_2400.000000_um 2 5080 0)
)
(image Resistor_SMD:R_0603_1608Metric
(outline (polygon signal 0 1475 -725 -1475 -725 -1475 725 1475 725))
(outline (path signal 120 -237.258 522.5 237.258 522.5))
(outline (path signal 120 -237.258 -522.5 237.258 -522.5))
(outline (path signal 100 -800 412.5 800 412.5 800 -412.5 -800 -412.5 -800 412.5))
(pin RoundRect[T]Pad_800.000000x950.000000_200.761000_um_0.000000_0 1 -825 0)
(pin RoundRect[T]Pad_800.000000x950.000000_200.761000_um_0.000000_0 2 825 0)
)
(image Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical
(outline (polygon signal 0 1765 -4315 -1765 -4315 -1765 1765 1765 1765))
(outline (path signal 120 -1380 1380 0 1380))
(outline (path signal 120 -1380 0 -1380 1380))
(outline (path signal 120 -1380 -1270 -1380 -3920))
(outline (path signal 120 -1380 -1270 1380 -1270))
(outline (path signal 120 -1380 -3920 1380 -3920))
(outline (path signal 120 1380 -1270 1380 -3920))
(outline (path signal 100 -1270 635 -635 1270))
(outline (path signal 100 -1270 -3810 -1270 635))
(outline (path signal 100 -635 1270 1270 1270))
(outline (path signal 100 1270 1270 1270 -3810))
(outline (path signal 100 1270 -3810 -1270 -3810))
(pin Rect[A]Pad_1700.000000x1700.000000_um 1 0 0)
(pin Round[A]Pad_1700.000000_um 2 0 -2540)
)
(image Capacitor_SMD:C_0603_1608Metric
(outline (polygon signal 0 1475 -725 -1475 -725 -1475 725 1475 725))
(outline (path signal 120 -140.58 510 140.58 510))
(outline (path signal 120 -140.58 -510 140.58 -510))
(outline (path signal 100 -800 400 800 400 800 -400 -800 -400 -800 400))
(pin RoundRect[T]Pad_900.000000x950.000000_225.856000_um_0.000000_0 1 -775 0)
(pin RoundRect[T]Pad_900.000000x950.000000_225.856000_um_0.000000_0 2 775 0)
)
(image "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm"
(outline (polygon signal 0 2195 2455 3695 2455 3695 -2455 2195 -2455 2195 -2695
-2195 -2695 -2195 -2455 -3695 -2455 -3695 2455 -2195 2455
-2195 2695 2195 2695))
(outline (path signal 120 -2060 2560 2060 2560))
(outline (path signal 120 -2060 2465 -2060 2560))
(outline (path signal 120 -2060 -2560 -2060 -2465))
(outline (path signal 120 2060 2560 2060 2465))
(outline (path signal 120 2060 -2465 2060 -2560))
(outline (path signal 120 2060 -2560 -2060 -2560))
(pin RoundRect[T]Pad_1950.000000x600.000000_150.571000_um_0.000000_0 1 -2475 1905)
(pin RoundRect[T]Pad_1950.000000x600.000000_150.571000_um_0.000000_0 2 -2475 635)
(pin RoundRect[T]Pad_1950.000000x600.000000_150.571000_um_0.000000_0 3 -2475 -635)
(pin RoundRect[T]Pad_1950.000000x600.000000_150.571000_um_0.000000_0 4 -2475 -1905)
(pin RoundRect[T]Pad_1950.000000x600.000000_150.571000_um_0.000000_0 5 2475 -1905)
(pin RoundRect[T]Pad_1950.000000x600.000000_150.571000_um_0.000000_0 6 2475 -635)
(pin RoundRect[T]Pad_1950.000000x600.000000_150.571000_um_0.000000_0 7 2475 635)
(pin RoundRect[T]Pad_1950.000000x600.000000_150.571000_um_0.000000_0 8 2475 1905)
)
(padstack Round[A]Pad_1700.000000_um
(shape (circle F.Cu 1700))
(shape (circle B.Cu 1700))
(attach off)
)
(padstack Round[A]Pad_2400.000000_um
(shape (circle F.Cu 2400))
(shape (circle B.Cu 2400))
(attach off)
)
(padstack RoundRect[A]Pad_2400.000000x2400.000000_250.952000_um_0.000000_0
(shape (polygon F.Cu 0 -1200.95 949.999 -1181.85 1046.03 -1127.45 1127.45 -1046.03 1181.85
-949.999 1200.95 949.999 1200.95 1046.03 1181.85 1127.45 1127.45
1181.85 1046.03 1200.95 949.999 1200.95 -949.999 1181.85 -1046.03
1127.45 -1127.45 1046.03 -1181.85 949.999 -1200.95 -949.999 -1200.95
-1046.03 -1181.85 -1127.45 -1127.45 -1181.85 -1046.03 -1200.95 -949.999
-1200.95 949.999))
(shape (polygon B.Cu 0 -1200.95 949.999 -1181.85 1046.03 -1127.45 1127.45 -1046.03 1181.85
-949.999 1200.95 949.999 1200.95 1046.03 1181.85 1127.45 1127.45
1181.85 1046.03 1200.95 949.999 1200.95 -949.999 1181.85 -1046.03
1127.45 -1127.45 1046.03 -1181.85 949.999 -1200.95 -949.999 -1200.95
-1046.03 -1181.85 -1127.45 -1127.45 -1181.85 -1046.03 -1200.95 -949.999
-1200.95 949.999))
(attach off)
)
(padstack RoundRect[T]Pad_800.000000x950.000000_200.761000_um_0.000000_0
(shape (polygon F.Cu 0 -400.761 275 -385.479 351.828 -341.959 416.959 -276.828 460.479
-199.999 475.76 200 475.761 276.828 460.479 341.959 416.959
385.479 351.828 400.76 274.999 400.761 -275 385.479 -351.828
341.959 -416.959 276.828 -460.479 199.999 -475.76 -200 -475.761
-276.828 -460.479 -341.959 -416.959 -385.479 -351.828 -400.76 -274.999
-400.761 275))
(attach off)
)
(padstack RoundRect[T]Pad_900.000000x950.000000_225.856000_um_0.000000_0
(shape (polygon F.Cu 0 -450.856 250 -433.664 336.431 -384.704 409.704 -311.431 458.664
-225 475.856 225 475.856 311.431 458.664 384.704 409.704
433.664 336.431 450.856 250 450.856 -250 433.664 -336.431
384.704 -409.704 311.431 -458.664 225 -475.856 -225 -475.856
-311.431 -458.664 -384.704 -409.704 -433.664 -336.431 -450.856 -250
-450.856 250))
(attach off)
)
(padstack RoundRect[T]Pad_1950.000000x600.000000_150.571000_um_0.000000_0
(shape (polygon F.Cu 0 -975.571 150 -964.109 207.621 -931.47 256.47 -882.621 289.109
-824.999 300.57 825 300.571 882.621 289.109 931.47 256.47
964.109 207.621 975.57 149.999 975.571 -150 964.109 -207.621
931.47 -256.47 882.621 -289.109 824.999 -300.57 -825 -300.571
-882.621 -289.109 -931.47 -256.47 -964.109 -207.621 -975.57 -149.999
-975.571 150))
(attach off)
)
(padstack Rect[A]Pad_1700.000000x1700.000000_um
(shape (rect F.Cu -850 -850 850 850))
(shape (rect B.Cu -850 -850 850 850))
(attach off)
)
(padstack "Via[0-1]_600:300_um"
(shape (circle F.Cu 600))
(shape (circle B.Cu 600))
(attach off)
)
)
(network
(net CANL
(pins J1-1 R1-1 U1-6)
)
(net TERM_L
(pins R1-2 R2-1 R4-2)
)
(net 3V3
(pins J2-1 R3-1 U1-3)
)
(net GND
(pins J2-2 R5-2 C1-2 U1-2)
)
(net TERM_H
(pins R2-2 R4-1 C1-1)
)
(net Rs
(pins J1-2 R5-1 U1-8)
)
(net D
(pins R3-2 U1-1)
)
(net R
(pins U1-4)
)
(net CANH
(pins U1-7)
)
(class kicad_default 3V3 CANH CANL D GND PWR_FLAG R Rs TERM_H TERM_L
(circuit
(use_via "Via[0-1]_600:300_um")
)
(rule
(width 200)
(clearance 200)
)
)
)
(wiring
)
)
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