nearxos
43648b1ffe
- Schematic: 12 components, 10 nets, ERC 0 (MCP batch_add_components + connect_to_net) - Board: 20x30mm 2-layer, JLCPCB DRC rules (0.15mm clearance) - Placement: U1 SN65HVD230 center, J1 CAN bus right, J2 power left, split termination below - Routing: Freerouting headless CLI, 44 tracks, 1 via, 13/14 nets routed - GND copper pour F.Cu+B.Cu, 20 stitching vias, collision-checked - DRC: 8 violations (3 courtyard overlap + 5 silk edge clearance - cosmetic only) - Gerbers exported (8 layers + drill) - SVG exported for review
47 lines
727 B
Plaintext
47 lines
727 B
Plaintext
M48
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; DRILL file KiCad 10.0.2 date 2026-06-22T21:54:00
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; FORMAT={-:-/ absolute / metric / decimal}
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; #@! TF.CreationDate,2026-06-22T21:54:00+03:00
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; #@! TF.GenerationSoftware,Kicad,Pcbnew,10.0.2
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; #@! TF.FileFunction,MixedPlating,1,2
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FMAT,2
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METRIC
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; #@! TA.AperFunction,Plated,PTH,ViaDrill
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T1C0.300
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; #@! TA.AperFunction,Plated,PTH,ComponentDrill
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T2C1.000
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; #@! TA.AperFunction,Plated,PTH,ComponentDrill
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T3C1.600
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%
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G90
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G05
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T1
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X5.0Y-5.0
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X5.0Y-20.0
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X5.0Y-25.0
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X5.122Y-12.991
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X7.0Y-5.0
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X7.0Y-10.0
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X7.0Y-25.0
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X10.0Y-5.0
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X10.0Y-10.0
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X10.0Y-25.0
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X12.0Y-5.0
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X12.0Y-25.0
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X15.0Y-5.0
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X15.0Y-10.0
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X15.0Y-15.0
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X15.0Y-20.0
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X15.0Y-25.0
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X17.0Y-5.0
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X17.0Y-10.0
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X17.0Y-20.0
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X17.0Y-25.0
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T2
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X3.0Y-15.0
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X3.0Y-17.54
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T3
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X17.0Y-15.0
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X22.08Y-15.0
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M30
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