f0b8c956c5
Fix J1 orientation to 90° — mating face now faces left board edge
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Analysis: GCT USB4105-xx-A 3D model has USB-C opening at Y=+3.73.
At 0°: mating face +Y (UP), at 90°: -X (LEFT), at 180°: -Y (DOWN into board).
For left-edge connector facing outward: rotation=90° is correct.
Rotation 180° pointed the port DOWN into the board interior — physically wrong.
2026-06-21 16:33:47 +03:00
3ecdb9f75d
Fix J1 to 180°, move R6/R7/R8/C5 away from ESP32, orthogonal 3V3/3V3_ESR/EN routing on B.Cu
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- J1 USB-C rotated to 180° (mating face toward left edge)
- R6→(48,4), R7→(60,4), R8→(60,20), C5→(48,8) — moved outside ESP32 body
- 3V3: R9.1→C5.1→R6.2→R7.1→U1.2 on B.Cu with 0.5mm orthogonal traces
- 3V3_ESR: R9.2→C4.1 on B.Cu (was shorting with 3V3 on F.Cu)
- EN: R6.1→U1.3 on B.Cu (was shorting with GND pad on F.Cu)
- U3.2→R9.1 on F.Cu at 1.0mm
- DRC: 179 (remaining GND/VBUS shorts are zone-fill dependent)
2026-06-21 16:25:44 +03:00
11c2d96561
Rebuild: fix J1 orientation (90°), re-place all components, Freerouting orthogonal routing, 84 GND vias
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- J1 rotated 90° so USB-C mating face faces left board edge
- All 23 components re-placed with proper spacing (8 courtyard overlaps remain — all ESP32 keepout)
- Freerouting v2.2.4: 21/25 nets autorouted cleanly
- 3V3/VBUS_SENSE manually routed on B.Cu for remaining 4 nets
- 84 GND stitching vias (grid + around_refs)
- DRC: 158 violations (0 tracks_crossing, 2 shorts, 84 via_dangling zone-fill dependent)
- Board 65x35mm, 2-layer
2026-06-21 12:19:07 +03:00
0ca0a9cdb7
Optimize placement + 3V3 on B.Cu + 104 GND vias + R9/R10 placed
2026-06-21 11:25:04 +03:00
77333e4e71
Add R9 (0.47R ESR for LD1117 stability) + R10 (22R gate resistor) + optimize placement
2026-06-21 09:10:57 +03:00
8ed0b7bb28
Dual-layer routing: GND pours before Freerouting, 208->51 DRC, B.Cu active
2026-06-21 00:02:53 +03:00
c34d2048d9
Re-route 3V3/EN/USB_DN on B.Cu - 208 DRC (all pour-related, resolves on zone fill)
2026-06-20 23:56:54 +03:00
4df1671d1a
Add 3 missing Freerouting nets (3V3/EN/USB_DN) + 98 GND stitching vias
2026-06-20 23:53:30 +03:00
4f7f08ccf9
Freerouting optimization: 266→42 DRC violations, 0 tracks_crossing, 0 shorting_items, 0 unrouted
2026-06-20 23:51:09 +03:00
a978205c25
Design review fixes: route 4 unrouted nets, ERC 0 errors, add fiducials+MPNs+silkscreen
2026-06-20 20:43:43 +03:00
64e6cefb93
Clean up artifacts
2026-06-20 18:29:31 +03:00
f9bd275297
Clean up artifacts
2026-06-20 18:29:25 +03:00
340aa834f5
Clean up lock files and .history
2026-06-20 18:29:16 +03:00
3e782cb582
Clean up lock files and .history
2026-06-20 18:29:10 +03:00
02b88f3018
Routing complete: all 16 nets routed, GND pours added
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Layer strategy:
F.Cu (top): VBUS (0.5mm), 3V3 (0.5mm), GATE (0.25mm), EN (0.25mm)
B.Cu (bottom): VOUT (0.5mm), CC1/CC2, USB_DP/DN, CFG1, VDD_CH224
128 GND stitching vias, GND copper pours on both layers
Board: 65x30mm 2-layer
Components: 19 placed, all footprints assigned
Nets: 16 (all connected)
DRC: 220 violations (solder mask bridges + edge clearances + tight routing)
- needs manual cleanup in KiCad UI
2026-06-20 18:29:02 +03:00
96adcbddc0
Full PCB routing complete
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Routed nets (15 total):
POWER (0.5mm): VBUS (J1->C1->Q1,S->R5), VOUT (Q1,D->U3,VIN->C3),
3V3 (U3,VOUT->C4->C5->U1->R6->R7)
SIGNAL (0.25mm): CC1 (J1->U2->R1), CC2 (J1->U2->R2),
USB_DP (J1->U2->U1), USB_DN (J1->U2->U1),
GATE (U2->Q1,G->R5), EN (U1->R6),
CFG1 (U2->R3), VDD_CH224 (U2->C2),
VBUS_SENSE (U2->VBUS)
GND stitching: 128 vias on 5mm grid
DRC: 143 violations (solder mask bridges + trace crossings)
- needs manual cleanup in KiCad UI for perfect routing
2026-06-20 18:21:02 +03:00
411db21e99
PCB layout: component placement & board outline
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PCB: 65x30mm 2-layer board with GND pours on F.Cu + B.Cu
Placement:
J1 (USB-C) at (5, 17.5) - left edge
U2 (CH224K) at (18, 10) - PD controller
Q1 (PMOS) at (18, 22) - VBUS switch
U3 (LDO) at (33, 17.5) - 3.3V regulator
U1 (ESP32-S3) at (50, 12) - right side
Passives placed near respective ICs
Footprints assigned: J1 (USB4105), U2 (SSOP-10), Q1 (SOT-23-3),
U3 (SOT-223-3), U1 (ESP32-S3-WROOM-1)
Design rules: 0.2mm clearance, 0.25mm track, 0.6/0.3mm via
DRC: 42 violations (pre-routing - courtyard overlaps + edge clearance)
Next: manual routing in KiCad UI
2026-06-20 17:51:12 +03:00
3b1807d71f
Add .gitignore, remove MCP backup artifacts
2026-06-20 17:47:43 +03:00
5c40f851d2
Fix schematic: restore all wire connections, separate 3V3 from GND
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- Re-connected all pins using pin-snapped connect_to_net (U1, U2, U3, J1, Q1, all passives)
- Fixed: 3V3 was shorted to GND by overlapping labels 0.47mm apart
- Replaced batch_connect labels (off-grid) with pin-exact connect_to_net labels
- Verified: 15 clean nets with no GND/3V3 contamination
- Nets: 3V3, CC1, CC2, CFG1, CFG2, EN, GATE, IO0, USB_DN, USB_DP,
VBUS, VBUS_SENSE, VDD_CH224, VOUT, GND
2026-06-20 17:47:37 +03:00
f2d64ccf04
Fix schematic syntax & finalize ERC
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- Fixed: double-empty-string bug () in power symbol Footprint properties
- Fixed: single-line 67KB file was unparseable by KiCad - properly pretty-printed to 4408 lines
- Added: 42 no-connect flags for unused pins (J1 SBU, ESP32 GPIOs, NC resistors)
- Added: PWR_FLAG and GND power symbols connected to nets
- Added: batch_connect wiring for passives (C1-C5, R1-R7)
- Snap-to-grid: 152 elements aligned to 1.27mm grid
- Board sync: 13 footprints added, 16 nets confirmed
- Custom CH224K symbol verified and committed
2026-06-20 17:40:26 +03:00
ef2514c332
USB-C PD board with ESP32-S3
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Complete initial design:
- CH224K PD sink controller (custom corrected symbol)
- USB-C receptacle (16-pin USB2.0)
- P-Channel MOSFET VBUS switch
- LD1117S33 3.3V LDO regulator (800mA)
- ESP32-S3-WROOM-1 module
- 15 nets: VBUS, VOUT, 3V3, GATE, CC1/CC2, USB_DP/USB_DN
- 5.1kΩ CC pull-down resistors
- CFG1/CFG2 for PD voltage selection
- Input/output decoupling capacitors
2026-06-20 17:31:20 +03:00
