USB_PD_ESP32S3

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nearxos 411db21e99 PCB layout: component placement & board outline

PCB: 65x30mm 2-layer board with GND pours on F.Cu + B.Cu
Placement:
  J1 (USB-C) at (5, 17.5) - left edge
  U2 (CH224K) at (18, 10) - PD controller
  Q1 (PMOS) at (18, 22) - VBUS switch
  U3 (LDO) at (33, 17.5) - 3.3V regulator
  U1 (ESP32-S3) at (50, 12) - right side
  Passives placed near respective ICs
Footprints assigned: J1 (USB4105), U2 (SSOP-10), Q1 (SOT-23-3),
  U3 (SOT-223-3), U1 (ESP32-S3-WROOM-1)
Design rules: 0.2mm clearance, 0.25mm track, 0.6/0.3mm via
DRC: 42 violations (pre-routing - courtyard overlaps + edge clearance)
Next: manual routing in KiCad UI

2026-06-20 17:51:12 +03:00

.gitignore

Add .gitignore, remove MCP backup artifacts

2026-06-20 17:47:43 +03:00

sym-lib-table

USB-C PD board with ESP32-S3

2026-06-20 17:31:20 +03:00

untitled-erc.rpt

Fix schematic syntax & finalize ERC

2026-06-20 17:40:26 +03:00

USB_PD_ESP32S3_drc_violations.json

PCB layout: component placement & board outline