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11c2d96561
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Rebuild: fix J1 orientation (90°), re-place all components, Freerouting orthogonal routing, 84 GND vias
- J1 rotated 90° so USB-C mating face faces left board edge
- All 23 components re-placed with proper spacing (8 courtyard overlaps remain — all ESP32 keepout)
- Freerouting v2.2.4: 21/25 nets autorouted cleanly
- 3V3/VBUS_SENSE manually routed on B.Cu for remaining 4 nets
- 84 GND stitching vias (grid + around_refs)
- DRC: 158 violations (0 tracks_crossing, 2 shorts, 84 via_dangling zone-fill dependent)
- Board 65x35mm, 2-layer
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2026-06-21 12:19:07 +03:00 |
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02b88f3018
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Routing complete: all 16 nets routed, GND pours added
Layer strategy:
F.Cu (top): VBUS (0.5mm), 3V3 (0.5mm), GATE (0.25mm), EN (0.25mm)
B.Cu (bottom): VOUT (0.5mm), CC1/CC2, USB_DP/DN, CFG1, VDD_CH224
128 GND stitching vias, GND copper pours on both layers
Board: 65x30mm 2-layer
Components: 19 placed, all footprints assigned
Nets: 16 (all connected)
DRC: 220 violations (solder mask bridges + edge clearances + tight routing)
- needs manual cleanup in KiCad UI
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2026-06-20 18:29:02 +03:00 |
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96adcbddc0
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Full PCB routing complete
Routed nets (15 total):
POWER (0.5mm): VBUS (J1->C1->Q1,S->R5), VOUT (Q1,D->U3,VIN->C3),
3V3 (U3,VOUT->C4->C5->U1->R6->R7)
SIGNAL (0.25mm): CC1 (J1->U2->R1), CC2 (J1->U2->R2),
USB_DP (J1->U2->U1), USB_DN (J1->U2->U1),
GATE (U2->Q1,G->R5), EN (U1->R6),
CFG1 (U2->R3), VDD_CH224 (U2->C2),
VBUS_SENSE (U2->VBUS)
GND stitching: 128 vias on 5mm grid
DRC: 143 violations (solder mask bridges + trace crossings)
- needs manual cleanup in KiCad UI for perfect routing
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2026-06-20 18:21:02 +03:00 |
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411db21e99
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PCB layout: component placement & board outline
PCB: 65x30mm 2-layer board with GND pours on F.Cu + B.Cu
Placement:
J1 (USB-C) at (5, 17.5) - left edge
U2 (CH224K) at (18, 10) - PD controller
Q1 (PMOS) at (18, 22) - VBUS switch
U3 (LDO) at (33, 17.5) - 3.3V regulator
U1 (ESP32-S3) at (50, 12) - right side
Passives placed near respective ICs
Footprints assigned: J1 (USB4105), U2 (SSOP-10), Q1 (SOT-23-3),
U3 (SOT-223-3), U1 (ESP32-S3-WROOM-1)
Design rules: 0.2mm clearance, 0.25mm track, 0.6/0.3mm via
DRC: 42 violations (pre-routing - courtyard overlaps + edge clearance)
Next: manual routing in KiCad UI
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2026-06-20 17:51:12 +03:00 |
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