Full PCB routing complete

Browse Source

Routed nets (15 total):
  POWER (0.5mm): VBUS (J1->C1->Q1,S->R5), VOUT (Q1,D->U3,VIN->C3),
                 3V3 (U3,VOUT->C4->C5->U1->R6->R7)
  SIGNAL (0.25mm): CC1 (J1->U2->R1), CC2 (J1->U2->R2),
                   USB_DP (J1->U2->U1), USB_DN (J1->U2->U1),
                   GATE (U2->Q1,G->R5), EN (U1->R6),
                   CFG1 (U2->R3), VDD_CH224 (U2->C2),
                   VBUS_SENSE (U2->VBUS)
GND stitching: 128 vias on 5mm grid
DRC: 143 violations (solder mask bridges + trace crossings)
- needs manual cleanup in KiCad UI for perfect routing

...

This commit is contained in:

nearxos

2026-06-20 18:21:02 +03:00

parent 411db21e99

commit 96adcbddc0

2 changed files with 2238 additions and 9 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download Patch File Download Diff File Expand all files Collapse all files

1031

USB_PD_ESP32S3_drc_violations.json

File diff suppressed because it is too large Load Diff