nearxos
43648b1ffe
- Schematic: 12 components, 10 nets, ERC 0 (MCP batch_add_components + connect_to_net) - Board: 20x30mm 2-layer, JLCPCB DRC rules (0.15mm clearance) - Placement: U1 SN65HVD230 center, J1 CAN bus right, J2 power left, split termination below - Routing: Freerouting headless CLI, 44 tracks, 1 via, 13/14 nets routed - GND copper pour F.Cu+B.Cu, 20 stitching vias, collision-checked - DRC: 8 violations (3 courtyard overlap + 5 silk edge clearance - cosmetic only) - Gerbers exported (8 layers + drill) - SVG exported for review
27 lines
626 B
Plaintext
27 lines
626 B
Plaintext
%TF.GenerationSoftware,KiCad,Pcbnew,10.0.2*%
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%TF.CreationDate,2026-06-22T21:53:59+03:00*%
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%TF.ProjectId,can-bus-transceiver,63616e2d-6275-4732-9d74-72616e736365,rev?*%
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%TF.SameCoordinates,Original*%
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%TF.FileFunction,Profile,NP*%
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%FSLAX46Y46*%
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G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
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G04 Created by KiCad (PCBNEW 10.0.2) date 2026-06-22 21:53:59*
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%MOMM*%
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%LPD*%
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G01*
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G04 APERTURE LIST*
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%TA.AperFunction,Profile*%
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%ADD10C,0.100000*%
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%TD*%
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G04 APERTURE END LIST*
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D10*
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X0Y0D02*
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X20000000Y0D01*
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X0Y-30000000D02*
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X0Y0D01*
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X20000000Y0D02*
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X20000000Y-30000000D01*
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X20000000Y-30000000D02*
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X0Y-30000000D01*
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M02*
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