can-bus-transceiver

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nearxos 43648b1ffe L2.3 CAN Bus Transceiver: complete PCB layout

- Schematic: 12 components, 10 nets, ERC 0 (MCP batch_add_components + connect_to_net)
- Board: 20x30mm 2-layer, JLCPCB DRC rules (0.15mm clearance)
- Placement: U1 SN65HVD230 center, J1 CAN bus right, J2 power left, split termination below
- Routing: Freerouting headless CLI, 44 tracks, 1 via, 13/14 nets routed
- GND copper pour F.Cu+B.Cu, 20 stitching vias, collision-checked
- DRC: 8 violations (3 courtyard overlap + 5 silk edge clearance - cosmetic only)
- Gerbers exported (8 layers + drill)
- SVG exported for review

2026-06-22 21:54:07 +03:00

.mcp-backups

L2.3 CAN Bus Transceiver: complete PCB layout

2026-06-22 21:54:07 +03:00

gerbers

L2.3 CAN Bus Transceiver: complete PCB layout

2026-06-22 21:54:07 +03:00

build_can_pcb.py

L2.3 CAN Bus Transceiver: complete PCB layout

2026-06-22 21:54:07 +03:00

can-bus-transceiver_drc_violations.json

L2.3 CAN Bus Transceiver: complete PCB layout