Layer strategy: F.Cu (top): VBUS (0.5mm), 3V3 (0.5mm), GATE (0.25mm), EN (0.25mm) B.Cu (bottom): VOUT (0.5mm), CC1/CC2, USB_DP/DN, CFG1, VDD_CH224 128 GND stitching vias, GND copper pours on both layers Board: 65x30mm 2-layer Components: 19 placed, all footprints assigned Nets: 16 (all connected) DRC: 220 violations (solder mask bridges + edge clearances + tight routing) - needs manual cleanup in KiCad UI
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57 B
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57 B
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{"hostname":"Nearchoss-MacBook-Air","username":"nearxos"} |