PCB layout: component placement & board outline

PCB: 65x30mm 2-layer board with GND pours on F.Cu + B.Cu
Placement:
  J1 (USB-C) at (5, 17.5) - left edge
  U2 (CH224K) at (18, 10) - PD controller
  Q1 (PMOS) at (18, 22) - VBUS switch
  U3 (LDO) at (33, 17.5) - 3.3V regulator
  U1 (ESP32-S3) at (50, 12) - right side
  Passives placed near respective ICs
Footprints assigned: J1 (USB4105), U2 (SSOP-10), Q1 (SOT-23-3),
  U3 (SOT-223-3), U1 (ESP32-S3-WROOM-1)
Design rules: 0.2mm clearance, 0.25mm track, 0.6/0.3mm via
DRC: 42 violations (pre-routing - courtyard overlaps + edge clearance)
Next: manual routing in KiCad UI

USB_PD_ESP32S3.kicad_pro

@@ -140,7 +140,7 @@
       },
       "rules": {
         "max_error": 0.005,
-        "min_clearance": 0.0,
+        "min_clearance": 0.2,
         "min_connection": 0.0,
         "min_copper_edge_clearance": 0.5,
         "min_groove_width": 0.0,
@@ -152,7 +152,7 @@
         "min_silk_clearance": 0.0,
         "min_text_height": 0.8,
         "min_text_thickness": 0.08,
-        "min_through_hole_diameter": 0.3,
+        "min_through_hole_diameter": 0.25,
         "min_track_width": 0.2,
         "min_via_annular_width": 0.1,
         "min_via_diameter": 0.5,