Detects wire segments with at least one dangling endpoint — an endpoint
not connected to a component pin, net label, or another wire. These
cause ERC 'wire end unconnected' violations and are a common symptom of
incomplete routing or stray stub wires.
Algorithm uses exact KiCad IU (10 000 IU/mm) coordinate matching,
consistent with wire_connectivity.py:
1. Build an endpoint-frequency map for all wires (IU precision)
2. Collect anchored IU points: component pins (via PinLocator),
net labels / global_labels, power symbol pins
(via _parse_virtual_connections)
3. An endpoint is dangling when it is touched by exactly one wire AND
is not an anchored point; the containing wire is reported
Does not require the KiCad UI to be running.
Changes:
python/commands/schematic_analysis.py — find_orphaned_wires() function
python/kicad_interface.py — handler + route registration
python/schemas/tool_schemas.py — MCP schema entry
src/tools/schematic.ts — TypeScript server.tool() call
tests/test_schematic_analysis.py — 7 integration tests
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
add_schematic_net_label now accepts optional componentRef + pinNumber to
snap the label directly to the exact pin endpoint via PinLocator, removing
all approximation risk. The response always includes actual_position and,
when snapping was used, snapped_to_pin — so the caller gets confirmation
of exactly where the label landed.
connect_to_net return type changed from bool to Dict, returning
pin_location, label_location, and wire_stub on success so agents no
longer need a separate verification call to confirm placement.
connect_passthrough updated to check result.get("success") against the
new dict return. tool_schemas.py and schematic.ts updated to match
(position is now optional, componentRef/pinNumber/labelType/orientation
added, connect_to_net schema field names corrected).
17 new unit tests in tests/test_net_label_pin_snapping.py.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Previously the path argument to create_schematic() was accepted by the
tool schema but silently ignored in SchematicManager.create_schematic()
(python/commands/schematic.py). The schematic file was always written
using only the bare filename, resolving to the MCP server's working
directory.
On systems where that directory is not writable (e.g. Program Files,
OneDrive-synced folders) this caused:
[Errno 13] Permission denied: 'myproject.kicad_sch'
Fix:
- Add path: Optional[str] = None parameter to SchematicManager.create_schematic()
- Compute output_path as os.path.join(path, base_name) when path is given
- Forward the resolved path from _handle_create_schematic() into create_schematic()
Tests: added tests/test_create_schematic_path.py with three unit tests
covering: path respected, no-path fallback, and no double-suffix on .kicad_sch names.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Add type annotations to all previously untyped functions and remove 9
suppressed error codes (call-arg, assignment, return-value, operator,
has-type, dict-item, misc, list-item, annotation-unchecked) by fixing
the underlying type issues.
Add [[tool.mypy.overrides]] with ignore_missing_imports for KiCAD-specific
modules (pcbnew, sexpdata, skip, cairosvg, kipy, PIL) so the pre-commit
mypy hook passes in its isolated venv. Add types-requests and pytest to
additional_dependencies in .pre-commit-config.yaml.
Also fixes several real bugs uncovered by stricter checks: incorrect static
calls to instance methods in swig_backend, wrong return type on get_size,
missing value param in BoardAPI.place_component, variable shadowing in
kicad_process.py, unqualified LibraryManager reference in kicad_interface,
and missing top-level Path import.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
The TS<->Python communication channel uses stdout for JSON responses.
pcbnew's C++ SWIG layer can write warnings and diagnostics directly to
C-level stdout (fd 1), corrupting the JSON framing. The TS parser then
never sees valid JSON and the command times out after 30 seconds.
Three changes fix this:
1. Python stdout redirect: In main(), save the original stdout fd for
exclusive JSON response use, then redirect fd 1 to stderr so all
pcbnew C++ output goes to logs instead of the response pipe.
2. Robust TS JSON parser: tryParseResponse() now uses newline-delimited
parsing as a fallback. The Python side writes single-line JSON
terminated by \n; the parser uses this as the completion signal
instead of brace-matching, which prevents premature resolution of
truncated chunked responses. Non-JSON preamble lines are logged
and stripped.
3. Fix stray print() calls: Converted print() to logger in
component_schematic.py and library_schematic.py so they don't
leak to stdout during normal operations.
Also adds sync_schematic_to_board to the longRunningCommands list for
an appropriate timeout value.
When moving a schematic component whose pins directly touch pins of
stationary components (no wire segment, just pin-to-pin contact),
synthesize bridge wires to preserve the electrical connection after
the move. Also fixes duplicate-pin-position collision in old_to_new
map and updates symbol reference assignment to use setAllReferences.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
When moving a schematic component, connected wires are stretched/shifted
to follow the component (like KiCAD's drag behaviour), preserving
connectivity instead of leaving dangling wire stubs.
Also fixes property labels (value, reference, etc.) so they shift with
the symbol rather than staying at their original positions.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Add isort configuration (profile=black, line_length=100) to pyproject.toml,
add isort pre-commit hook, and auto-sort imports across all Python source files.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Add [tool.black] config to pyproject.toml and Black hook to
.pre-commit-config.yaml (rev 26.3.1), then auto-format all Python
source and test files with line-length=100, target-version=py310.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Add .pre-commit-config.yaml with pre-commit-hooks v5.0.0 (trailing
whitespace, end-of-file fixer, yaml/json checks, large file guard,
merge conflict detection). Add minimal pyproject.toml. Auto-fix
trailing whitespace and missing end-of-file newlines across the
codebase.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Replace /home/chris/... absolute paths with Path(__file__)-relative
equivalents in wire_manager.py and pin_locator.py so the test
scripts work on any machine.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Replace inline Symbol() allocations with the existing _SYM_WIRE/_SYM_PTS/_SYM_XY
constants and new _SYM_AT/_SYM_LABEL constants for consistency.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Adds an optional `layer` parameter (e.g., 'F.Cu', 'B.Cu') to the
move_component tool. When specified, the component is flipped to
the target layer if it's not already on it. The response now also
includes the component's layer after the move.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
fix: JLCPCB database download and FTS search
Thanks! you rock. JLCPCB parts things has been a headache. I will look over the whole implementation this weekend.
- Rename add_schematic_connection → add_schematic_wire with waypoints[] parameter
- Add snapToPins (default true) to snap wire endpoints to nearest pin
- Expose add_schematic_junction as an MCP tool
- Break existing wires at new wire endpoints for T-junction support
- Remove orphaned add_connection / add_wire / get_pin_location from ConnectionManager
- Update tool registry to reflect renamed schematic tools in TS layer
- Add 76 tests for wire/junction handler dispatch, schema validation, and WireManager corner cases
- Apply Black and Prettier formatting to changed files
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Remove the 0.5mm query tolerance in favour of exact integer-unit matching
on all coordinate lookups (seed, label bridging, pin matching), mirroring
KiCad's own connectivity algorithm. Callers must supply exact wire endpoint
coordinates (e.g. from list_schematic_wires).
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Update tool description and Python docstring to make clear that the
query point must be at a wire endpoint or junction — midpoints of
wire segments are not matched.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Shared-endpoint adjacency already connects all wires meeting at the same
point, making explicit junction handling a no-op duplicate.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Move wire connectivity logic from _handle_get_wire_connections into
commands/wire_connectivity.py. Use KiCad's internal integer unit system
(10,000 IU/mm) with exact coordinate matching instead of tolerance-based
float comparison, mirroring how KiCad itself determines connectivity.
Key improvements:
- Exact integer matching for wire endpoints (O(1) dict lookup vs O(n) grid scan)
- Junction support for T-connections
- Multi-unit symbol support (removed incorrect processed_refs dedup)
- Single public API: get_wire_connections()
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
The JLCSearch API (jlcsearch.tscircuit.com) /components/list.json
endpoint ignores the offset parameter, returning the same 100 parts
on every request. This caused download_jlcpcb_database to loop
indefinitely, importing duplicate data for hours while blocking the
single-threaded Python process.
- Add download_jlcpcb.py: standalone script that downloads the
pre-built jlcparts database from yaqwsx/jlcparts GitHub Pages
(~1GB compressed, 7M+ parts, completes in ~4 minutes)
- Fix FTS search: add prefix wildcards to search terms so partial
MPN matches work (e.g. "BQ25895" now finds "BQ25895RTWR")
Library symbols use y-up coordinates while schematics use y-down. The
_transform_local_point function was not negating y, causing asymmetric
symbols (e.g. power:VEE) to have their bounding boxes computed in the
wrong direction — missing overlaps with adjacent components.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
KiCad's native ERC already checks for unconnected pins with better
accuracy (hierarchical sheets, bus connections, custom rules). Remove
the reimplemented version and its dead helper _parse_no_connects.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Parse graphical elements (rectangle, polyline, circle, arc, bezier) from
lib_symbols definitions to compute accurate symbol bounding boxes instead
of relying on pin positions with hardcoded degenerate expansion. This
fixes bbox accuracy for ICs (previously too small), tiny 2-pin passives
(previously too large), and single-pin symbols.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Eliminate repeated file parsing by extracting _extract_lib_symbols helper
that walks already-parsed sexp_data once instead of re-reading the file
per symbol via PinLocator. Support diagonal wire overlap detection using
cross-product parallelism and 1D projection. Fix wire region inclusion to
use AABB intersection for pass-through wires. Normalize view region
coordinates. Clarify tolerance docstrings across Python, TS, and schema.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Wires that start at a component pin but continue through the body were
incorrectly suppressed as "valid connections." Now nudges the pin endpoint
toward the other end and re-tests intersection — if the shortened segment
still hits the bbox, the wire passes through and is flagged.
Renamed the tool from check_wire_collisions to find_wires_crossing_symbols
across all layers (Python, handler, schema, TypeScript) to clarify that it
finds wires crossing over component symbols, which is unacceptable in
schematics.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
The overlap detection was comparing center-to-center Euclidean distance with
a 0.5mm tolerance, missing components whose bodies physically overlap but have
different centers (e.g. a resistor placed inside an opamp triangle). Now uses
AABB intersection on pin-derived bounding boxes, matching the approach already
used by check_wire_collisions. Extracted shared bbox logic into
_compute_symbol_bbox_direct and _aabb_overlap helpers.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Previously, the endpoint suppression logic skipped any wire where at least
one endpoint touched a pin, hiding the case where both endpoints are pins
of the same component (a direct pin-to-pin short through the body).
Replace the single endpoint_matches_pin loop with separate start_at_pin /
end_at_pin checks; suppress only when exactly one endpoint is at a pin.
Add regression test to cover this case.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
The same reference-lookup bug fixed in check_wire_collisions (where
PinLocator.get_all_symbol_pins always resolves to the first symbol
with a given reference) also affected:
- find_unconnected_pins: would check wrong pin positions for all
unannotated components after the first, producing false connected/
unconnected reports.
- get_elements_in_region: would return wrong pin coordinates for
unannotated components in the queried region.
Both now use _compute_pin_positions_direct (fetching pin defs by
lib_id and applying each symbol's own position/rotation/mirror),
matching the fix already applied to check_wire_collisions.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
PinLocator.get_all_symbol_pins resolves symbols by reference designator,
so when multiple components share the same unannotated reference (e.g. "Q?"),
it always returned the first match's pin positions. Every duplicate then
got an identical bounding box, causing a single wire to be flagged against
all N instances instead of only the ones it actually crosses.
Fix: add _compute_pin_positions_direct() that computes absolute pin positions
directly from each symbol's own (at x y rotation) and (mirror ...) data plus
pin definitions fetched by lib_id — no reference-name lookup involved.
Also extend _parse_symbols to capture mirror_x/mirror_y flags.
Add regression test: two "R?" at different positions, wire crossing only
one → must produce 0 collisions against the far-away component.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Add five new read-only schematic analysis MCP tools:
- get_schematic_view_region: export cropped schematic region as PNG/SVG
- find_unconnected_pins: list pins with no wire/label/power connection
- find_overlapping_elements: detect duplicate symbols, stacked labels, collinear wire overlaps
- get_elements_in_region: list all symbols/wires/labels in a bounding box
- check_wire_collisions: detect wires passing through component bodies
Includes Python handler dispatch, tool schemas, TypeScript server bindings,
the schematic_analysis command module, and a full test suite (28 tests passing).
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Auto-detects runtime: Java 21+ direct or Docker/Podman fallback.
Discovers docker/podman via PATH instead of hardcoding.
README includes one-time setup with JAR download + Docker pull.
31 tests covering both execution modes.
4 new MCP tools: autoroute (full DSN→Freerouting→SES pipeline),
export_dsn, import_ses, check_freerouting. Requires Java 11+ and
freerouting.jar. Includes 21 test cases and README usage examples.
- Add python/tests/conftest.py with MagicMock stubs for pcbnew/skip
- Add python/tests/test_schematic_tools.py with 29 tests covering
WireManager.delete_wire, WireManager.delete_label (unit + integration),
and parameter validation for all 11 new _handle_* methods
- Apply black formatting to component_schematic.py, wire_manager.py,
and kicad_interface.py
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
delete_schematic_net_label was using kicad-skip's write() which silently
discards in-memory _elements mutations. Replaced with WireManager.delete_label()
that uses the same sexpdata round-trip approach already used by delete_schematic_wire.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
kicad-skip's write() serializes from original parsed data, silently
discarding in-memory _elements mutations. Switch to the same sexpdata
approach used by add_wire: parse, find matching wire, delete the entry,
write back. Also adds WireManager.delete_wire() static method.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
ElementCollection in kicad-skip doesn't implement remove(), causing
'WireCollection object has no attribute remove' errors. Access the
underlying _elements list directly for wire, label, and symbol deletion.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
- Detects F.Cu<->B.Cu layer mismatch in route_pad_to_pad
- Splits route into: trace on start layer + via at midpoint + trace on end layer
- route_trace description warns: use route_pad_to_pad for cross-layer routing
- route_pad_to_pad description highlights automatic via insertion
Bug 1 — Rounded corners missing (src/tools/board.ts schema)
Symptom: Claude sends shape='rectangle' + radius=2.5, but the Zod schema
only listed 'rectangle', 'circle', 'polygon' as valid shapes. The JS
handler never passed cornerRadius through the IPC path, and Python only
generated arcs for shape='rounded_rectangle'. Result: 4 straight lines,
no arcs.
Fix: Added 'rounded_rectangle' and 'cornerRadius' to the Zod schema in
src/tools/board.ts so Claude can send the correct shape directly.
Also added a Python-side auto-upgrade: if shape='rectangle' and
cornerRadius>0, silently promote to 'rounded_rectangle' so legacy
callers still work (python/commands/board/outline.py).
Bug 2 — Board outline placed at (-w/2, -h/2) instead of (0, 0)
Symptom: A 30x30 mm board outline was placed centred at the origin
(start -15 -15) ... (end 15 15) instead of the expected top-left at
(0,0) → (30,30).
Root cause: src/tools/board.ts extracted x/y from params and renamed
them to centerX/centerY before forwarding to Python:
const { x, y, ...otherParams } = params;
callKicadScript('add_board_outline', { centerX: x, centerY: y, ...otherParams })
Python received centerX=0, centerY=0 and used that as the board centre,
placing the outline at (-15,-15)→(+15,+15).
Fix: Pass x/y directly as top-left corner coordinates. Python already
contains the correct logic: center = x + width/2, y + height/2. Removed
the incorrect rename in board.ts:
callKicadScript('add_board_outline', { shape, ...params })
Bug 3 — print() on stdout corrupted JSON-RPC protocol → Timeout
Symptom: Claude Desktop reported 'Timeout' for add_board_outline even
though Python completed the command in <5 ms. KiCAD was falsely launched.
Root cause: Debug print() statements written to stdout (the same channel
used for JSON-RPC responses) injected non-JSON lines into the protocol.
Node.js could not parse the response → timeout → Claude Desktop invented
a 'KiCAD UI required' workaround.
Fix: Removed all print() calls from outline.py. Logger.info/debug writes
to the log file (~/.kicad-mcp/logs/kicad_interface.log) and is safe.
Files changed:
src/tools/board.ts — Zod schema + removed centerX/centerY rename
python/commands/board/outline.py — auto-upgrade rectangle+radius, remove print()
