feat: walk all sub-sheets to build hierarchical pad→net map for sync
Hierarchical KiCad schematics store all components in sub-sheets; the top-level .kicad_sch only contains sheet references. The previous sync_schematic_to_board implementation called generate_netlist on the top-level file only, which has no components, so it always returned 0 pads assigned. Replace with _build_hierarchical_pad_net_map which: - rglobs all .kicad_sch files in the project directory - For each sheet, collects label positions from label, global_label, and hierarchical_label via skip.Schematic - Adds power symbol (#PWR/#FLG) positions using their Value as net name - Builds a wire adjacency graph and BFS-propagates net names through wire segments to reach pins not directly under a label - Calls PinLocator.get_all_symbol_pins to get absolute pin positions, then matches to the propagated net map within 0.5 mm tolerance Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
This commit is contained in:
Samuel Price
@@ -3056,6 +3056,148 @@ class KiCADInterface:
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logger.error(f"Error generating netlist: {e}")
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return {"success": False, "message": str(e)}
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def _build_hierarchical_pad_net_map(self, project_sch_path: str):
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"""Walk all .kicad_sch files in the project and build a {(ref, pin_num): net_name} map.
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Handles hierarchical schematics by scanning every sub-sheet file. Net names
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from global_label / hierarchical_label / local label / power symbols are all
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collected. Wire connectivity is traced via BFS so labels not placed directly
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on a pin endpoint still reach through wire segments.
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Returns: (pad_net_map, net_names_set)
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"""
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from collections import defaultdict
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from pathlib import Path
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from commands.pin_locator import PinLocator
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from skip import Schematic
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TOLERANCE = 0.5 # mm; schematic grid is 1.27 mm so 0.5 is safe
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def snap(x, y):
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"""Round to 2 dp to use exact dict lookup instead of O(n²) scan."""
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return (round(float(x), 2), round(float(y), 2))
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def nearby_net(pt, point_net, tol=TOLERANCE):
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"""Return net name for the nearest occupied grid point, or None."""
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x, y = pt
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# Try exact snap first (fast path)
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key = snap(x, y)
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if key in point_net:
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return point_net[key]
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# Slow fallback for off-grid placements
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for (lx, ly), name in point_net.items():
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if abs(x - lx) < tol and abs(y - ly) < tol:
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return name
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return None
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project_dir = Path(project_sch_path).parent
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pad_net_map: dict = {}
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all_net_names: set = set()
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pin_locator = PinLocator()
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sch_files = sorted(project_dir.rglob("*.kicad_sch"))
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logger.info(f"_build_hierarchical_pad_net_map: scanning {len(sch_files)} schematic files")
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for sch_path in sch_files:
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try:
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sch = Schematic(str(sch_path))
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except Exception as e:
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logger.warning(f"Could not load {sch_path}: {e}")
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continue
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# ── 1. Collect explicit label positions → net name ──────────────
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point_net: dict = {} # snap(x,y) -> net_name
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for attr in ("label", "global_label", "hierarchical_label"):
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for lbl in getattr(sch, attr, None) or []:
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try:
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pos = lbl.at.value
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name = lbl.value
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if name:
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k = snap(pos[0], pos[1])
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point_net[k] = name
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all_net_names.add(name)
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except Exception:
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pass
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# Power symbols (#PWR / #FLG): value property IS the net name; use pin 1 pos
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for sym in getattr(sch, "symbol", None) or []:
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try:
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ref = sym.property.Reference.value
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if not (ref.startswith("#PWR") or ref.startswith("#FLG")):
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continue
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net_name = sym.property.Value.value
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if not net_name:
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continue
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all_pins = pin_locator.get_all_symbol_pins(sch_path, ref)
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for _pin_num, (px, py) in all_pins.items():
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k = snap(px, py)
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point_net[k] = net_name
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all_net_names.add(net_name)
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except Exception:
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pass
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# ── 2. Build wire adjacency and BFS-propagate net names ──────────
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wire_segments = []
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for wire in getattr(sch, "wire", None) or []:
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try:
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pts = []
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for pt in wire.pts.xy:
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pts.append(snap(pt.value[0], pt.value[1]))
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if len(pts) >= 2:
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wire_segments.append(pts)
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except Exception:
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pass
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# Adjacency: connect endpoints of different segments that share a grid point
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point_adj: dict = defaultdict(set)
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for seg in wire_segments:
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# Connect consecutive points within the segment
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for i in range(len(seg) - 1):
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point_adj[seg[i]].add(seg[i + 1])
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point_adj[seg[i + 1]].add(seg[i])
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# All unique wire points
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all_wire_pts = set()
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for seg in wire_segments:
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all_wire_pts.update(seg)
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# BFS: propagate known net names through wire connections
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queue = [pt for pt in all_wire_pts if pt in point_net]
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visited = set(queue)
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while queue:
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pt = queue.pop()
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net = point_net[pt]
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for neighbor in point_adj[pt]:
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if neighbor not in point_net:
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point_net[neighbor] = net
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all_net_names.add(net)
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if neighbor not in visited:
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visited.add(neighbor)
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queue.append(neighbor)
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# ── 3. Match component pin positions to net names ────────────────
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for sym in getattr(sch, "symbol", None) or []:
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try:
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ref = sym.property.Reference.value
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if ref.startswith("#"):
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continue
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except Exception:
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continue
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pin_positions = pin_locator.get_all_symbol_pins(sch_path, ref)
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for pin_num, (px, py) in pin_positions.items():
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net = nearby_net((px, py), point_net)
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if net:
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pad_net_map[(ref, pin_num)] = net
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logger.info(
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f"_build_hierarchical_pad_net_map: {len(pad_net_map)} pin→net assignments, "
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f"{len(all_net_names)} unique nets"
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)
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return pad_net_map, all_net_names
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def _handle_sync_schematic_to_board(self, params: Dict[str, Any]) -> Dict[str, Any]:
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"""Sync schematic netlist to PCB board (equivalent to KiCAD F8 'Update PCB from Schematic').
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Reads net connections from the schematic and assigns them to the matching pads in the PCB.
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@@ -3100,24 +3242,8 @@ class KiCADInterface:
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"message": f"Schematic not found. Provide schematicPath. Tried: {schematic_path}",
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}
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# Generate netlist from schematic
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schematic = SchematicManager.load_schematic(schematic_path)
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if not schematic:
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return {"success": False, "message": "Failed to load schematic"}
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netlist = ConnectionManager.generate_netlist(schematic, schematic_path=schematic_path)
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# Build (reference, pad_number) -> net_name map
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pad_net_map = {} # {(ref, pin_str): net_name}
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net_names = set()
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for net_entry in netlist.get("nets", []):
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net_name = net_entry["name"]
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net_names.add(net_name)
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for conn in net_entry.get("connections", []):
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ref = conn.get("component", "")
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pin = str(conn.get("pin", ""))
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if ref and pin and pin != "unknown":
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pad_net_map[(ref, pin)] = net_name
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# Build hierarchical pad→net map (walks all sub-sheets)
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pad_net_map, net_names = self._build_hierarchical_pad_net_map(schematic_path)
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# Add all nets to board
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netinfo = board.GetNetInfo()
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