81 lines
2.8 KiB
Markdown
81 lines
2.8 KiB
Markdown
# ESP32-S3 Sensor Node — L2.1 Training Exercise
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## Project Setup
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1. **Open in KiCad 10.0+** — File → Open Project → `/Users/nearxos/Documents/KiCad/10.0/esp32-s3-sensor-node`
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2. **Schematic** — Already clean (ERC 0). View in Eeschema.
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3. **PCB Layout** — Needs routing. Create board in Pcbnew.
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## PCB Spec
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- **Size:** 65 × 40mm, 2-layer
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- **Stackup:** 1.6mm FR4, 1oz copper, HASL
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- **Design rules:** trace/space 0.15mm, drill 0.3mm, annular 0.15mm
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- **Target fab:** JLCPCB / PCBWay standard
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## Component Placement
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```
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Board: (0,0) bottom-left, (65,40) top-right
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Left edge (x≈5-15):
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J1 USB-C @ (7, 20) — left edge, USB mating face outward
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R7 CC1 pull-down @ (11, 28)
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R8 CC2 pull-down @ (11, 25)
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Lower-left (x≈15-25, y≈3-15):
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J3 PROG header @ (25, 3) — bottom edge
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R3 IO0 pull-up @ (16, 7)
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R4 IO12 pull-down @ (16, 12)
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Center-left (x≈20-30):
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U2 AMS1117-3.3 @ (20, 20) — regulator
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C5 10µF input @ (24, 17) — near U2 pin 3 (VI)
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C6 10µF output @ (24, 23) — near U2 pin 2 (VO)
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Center (x≈27-38):
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R2 EN pull-up @ (27, 32)
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C4 EN cap @ (26, 35)
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C1-C3 decoupling @ (30, 22-28) — near U1 3V3 pins
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U1 ESP32-S3 @ (38, 20) — main module
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Right side (x≈48-58):
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R5 SDA pull-up @ (48, 24)
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R6 SCL pull-up @ (48, 22)
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J2 I2C connector @ (56, 20) — right edge
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D1 Status LED @ (55, 34) — top-right edge
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R1 LED resistor @ (55, 30)
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```
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## Antenna Keepout
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- **Zone:** x > 46mm, y > 28mm (top-right corner)
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- No copper, no traces, no components in this area
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- The ESP32-S3-WROOM-1 module has its PCB antenna at the top-right corner
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## Routing Order
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1. **USB differential pair** — USB_D_P / USB_D_N: 90Ω impedance, length-matched
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- Width: ~0.3mm on 1.6mm FR4 (calc with fab's tool)
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- Gap: ~0.15mm
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- Route on top layer, GND reference on bottom
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2. **3V3 power** — 0.5mm traces from U2 VO to U1 3V3 pin + all 3V3 nodes
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3. **VBUS power** — 0.5mm from J1 to U2 VI
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4. **GND** — Copper pours on both layers with stitching vias
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5. **I2C** — SDA/SCL routed together, away from noisy traces
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6. **UART** — RXD0/TXD0 to J3
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7. **Strapping** — EN, IO0, IO12 to pull resistors
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8. **LED** — IO2_LED through R1 to D1
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## GND Pour Strategy
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- **B.Cu (bottom):** Full copper pour, entire board area
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- **F.Cu (top):** Full copper pour EXCEPT antenna keepout zone
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- **Antenna keepout:** Keepout zone polygon on both layers (no copper)
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- **Stitching vias:** Perimeter every 5mm, plus around module GND pads
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## Files
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| File | Description |
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|------|-------------|
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| `*.kicad_sch` | Schematic (ERC 0) |
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| `*.kicad_pcb` | PCB layout (empty, needs routing) |
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| `*.kicad_pro` | Project file |
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| `gen_schematic.py` | Python schematic generator |
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| `gen_pcb.py` | Python PCB generator (outline + placement) |
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