|
|
06db96cd57
|
L2.1 FINAL v2: Clean routing + 60 GND vias + copper pours
- Restored board from commit 71dd98f (clean state before trace deletion)
- Imported best Freerouting SES: 277 tracks, 12 vias
- GND copper pours F.Cu+B.Cu, zone fill confirmed
- 60 GND stitching vias placed (collision-aware, none in U1 keepout)
- DRC: 140 violations (40 keepout + 21 via_dangling + 12 overlap + cosmetic)
- Gerbers v3 exported: gerbers-v3/ with 11 files
- JLCPCB DRC rules: 0.15mm clearance, 0.3mm min drill
- Netlist: 20 components, 17 nets, all connected
|
2026-06-22 21:29:41 +03:00 |
|
|
|
541fad9b28
|
L2.1 FINAL: Complete PCB layout with routing, Gerbers, BOM
- Major cleanup: GND traces/stitching vias removed from U1 keepout area
- Re-exported all fabrication files via kicad-cli
- Gerbers: F.Cu, B.Cu, F/B.Mask, F/B.SilkS, F/B.Paste, Edge.Cuts
- Drill file: Excellon format
- BOM: 20 components, CSV formatted
- Pick-and-place: CSV, mm units, both sides
- DRC: 82 violations (zone-fill artifacts + edge clearance)
- 21 unconnected (GND vias needing zone fill - restore via SES import)
- All files in gerbers-v2/
- Netlist verified: 20 components, 17 nets connected
|
2026-06-22 21:27:37 +03:00 |
|
|
|
71dd98f2f8
|
L2.1 PCB layout: routed board with Freerouting, GND pours, 77 stitching vias, Gerbers exported
- Schematic rebuilt with MCP batch_add_and_connect (23 components, 17 nets)
- Board outline: 65×40mm, 2-layer, JLCPCB DRC rules (0.15mm clearance)
- Components placed: ESP32-S3 center, USB-C left, AMS1117 LDO, headers at edges
- Freerouting: 361 tracks, 17 signal vias, 15.7s autoroute
- GND copper pour on F.Cu + B.Cu, 77 stitching vias
- DRC: 208 violations (77 via_dangling = zone fill artifacts, resolve on KiCad GUI fill)
- Gerbers + drill + BOM + pick-and-place exported to gerbers/
- Netlist verified: 20 components, 16 nets all properly connected
|
2026-06-22 21:19:02 +03:00 |
|
