ESP32-S3 Sensor Node L2.1 — schematic ERC 0, PCB outline+placement, README

README.md

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+# ESP32-S3 Sensor Node — L2.1 Training Exercise
+
+## Project Setup
+
+1. **Open in KiCad 10.0+** — File → Open Project → `/Users/nearxos/Documents/KiCad/10.0/esp32-s3-sensor-node`
+2. **Schematic** — Already clean (ERC 0). View in Eeschema.
+3. **PCB Layout** — Needs routing. Create board in Pcbnew.
+
+## PCB Spec
+- **Size:** 65 × 40mm, 2-layer
+- **Stackup:** 1.6mm FR4, 1oz copper, HASL
+- **Design rules:** trace/space 0.15mm, drill 0.3mm, annular 0.15mm
+- **Target fab:** JLCPCB / PCBWay standard
+
+## Component Placement
+
+```
+Board: (0,0) bottom-left, (65,40) top-right
+
+Left edge (x≈5-15):
+  J1  USB-C         @ (7, 20)    — left edge, USB mating face outward
+  R7  CC1 pull-down @ (11, 28)
+  R8  CC2 pull-down @ (11, 25)
+
+Lower-left (x≈15-25, y≈3-15):
+  J3  PROG header   @ (25, 3)    — bottom edge
+  R3  IO0 pull-up   @ (16, 7)
+  R4  IO12 pull-down @ (16, 12)
+
+Center-left (x≈20-30):
+  U2  AMS1117-3.3   @ (20, 20)   — regulator
+  C5  10µF input    @ (24, 17)   — near U2 pin 3 (VI)
+  C6  10µF output   @ (24, 23)   — near U2 pin 2 (VO)
+
+Center (x≈27-38):
+  R2  EN pull-up    @ (27, 32)
+  C4  EN cap        @ (26, 35)
+  C1-C3 decoupling  @ (30, 22-28) — near U1 3V3 pins
+  U1  ESP32-S3      @ (38, 20)   — main module
+
+Right side (x≈48-58):
+  R5  SDA pull-up   @ (48, 24)
+  R6  SCL pull-up   @ (48, 22)
+  J2  I2C connector @ (56, 20)   — right edge
+  D1  Status LED    @ (55, 34)   — top-right edge
+  R1  LED resistor  @ (55, 30)
+```
+
+## Antenna Keepout
+- **Zone:** x > 46mm, y > 28mm (top-right corner)
+- No copper, no traces, no components in this area
+- The ESP32-S3-WROOM-1 module has its PCB antenna at the top-right corner
+
+## Routing Order
+1. **USB differential pair** — USB_D_P / USB_D_N: 90Ω impedance, length-matched
+   - Width: ~0.3mm on 1.6mm FR4 (calc with fab's tool)
+   - Gap: ~0.15mm
+   - Route on top layer, GND reference on bottom
+2. **3V3 power** — 0.5mm traces from U2 VO to U1 3V3 pin + all 3V3 nodes
+3. **VBUS power** — 0.5mm from J1 to U2 VI
+4. **GND** — Copper pours on both layers with stitching vias
+5. **I2C** — SDA/SCL routed together, away from noisy traces
+6. **UART** — RXD0/TXD0 to J3
+7. **Strapping** — EN, IO0, IO12 to pull resistors
+8. **LED** — IO2_LED through R1 to D1
+
+## GND Pour Strategy
+- **B.Cu (bottom):** Full copper pour, entire board area
+- **F.Cu (top):** Full copper pour EXCEPT antenna keepout zone
+- **Antenna keepout:** Keepout zone polygon on both layers (no copper)
+- **Stitching vias:** Perimeter every 5mm, plus around module GND pads
+
+## Files
+| File | Description |
+|------|-------------|
+| `*.kicad_sch` | Schematic (ERC 0) |
+| `*.kicad_pcb` | PCB layout (empty, needs routing) |
+| `*.kicad_pro` | Project file |
+| `gen_schematic.py` | Python schematic generator |
+| `gen_pcb.py` | Python PCB generator (outline + placement) |