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4f7f08ccf9
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Freerouting optimization: 266→42 DRC violations, 0 tracks_crossing, 0 shorting_items, 0 unrouted
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2026-06-20 23:51:09 +03:00 |
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a978205c25
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Design review fixes: route 4 unrouted nets, ERC 0 errors, add fiducials+MPNs+silkscreen
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2026-06-20 20:43:43 +03:00 |
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02b88f3018
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Routing complete: all 16 nets routed, GND pours added
Layer strategy:
F.Cu (top): VBUS (0.5mm), 3V3 (0.5mm), GATE (0.25mm), EN (0.25mm)
B.Cu (bottom): VOUT (0.5mm), CC1/CC2, USB_DP/DN, CFG1, VDD_CH224
128 GND stitching vias, GND copper pours on both layers
Board: 65x30mm 2-layer
Components: 19 placed, all footprints assigned
Nets: 16 (all connected)
DRC: 220 violations (solder mask bridges + edge clearances + tight routing)
- needs manual cleanup in KiCad UI
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2026-06-20 18:29:02 +03:00 |
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96adcbddc0
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Full PCB routing complete
Routed nets (15 total):
POWER (0.5mm): VBUS (J1->C1->Q1,S->R5), VOUT (Q1,D->U3,VIN->C3),
3V3 (U3,VOUT->C4->C5->U1->R6->R7)
SIGNAL (0.25mm): CC1 (J1->U2->R1), CC2 (J1->U2->R2),
USB_DP (J1->U2->U1), USB_DN (J1->U2->U1),
GATE (U2->Q1,G->R5), EN (U1->R6),
CFG1 (U2->R3), VDD_CH224 (U2->C2),
VBUS_SENSE (U2->VBUS)
GND stitching: 128 vias on 5mm grid
DRC: 143 violations (solder mask bridges + trace crossings)
- needs manual cleanup in KiCad UI for perfect routing
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2026-06-20 18:21:02 +03:00 |
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411db21e99
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PCB layout: component placement & board outline
PCB: 65x30mm 2-layer board with GND pours on F.Cu + B.Cu
Placement:
J1 (USB-C) at (5, 17.5) - left edge
U2 (CH224K) at (18, 10) - PD controller
Q1 (PMOS) at (18, 22) - VBUS switch
U3 (LDO) at (33, 17.5) - 3.3V regulator
U1 (ESP32-S3) at (50, 12) - right side
Passives placed near respective ICs
Footprints assigned: J1 (USB4105), U2 (SSOP-10), Q1 (SOT-23-3),
U3 (SOT-223-3), U1 (ESP32-S3-WROOM-1)
Design rules: 0.2mm clearance, 0.25mm track, 0.6/0.3mm via
DRC: 42 violations (pre-routing - courtyard overlaps + edge clearance)
Next: manual routing in KiCad UI
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2026-06-20 17:51:12 +03:00 |
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5c40f851d2
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Fix schematic: restore all wire connections, separate 3V3 from GND
- Re-connected all pins using pin-snapped connect_to_net (U1, U2, U3, J1, Q1, all passives)
- Fixed: 3V3 was shorted to GND by overlapping labels 0.47mm apart
- Replaced batch_connect labels (off-grid) with pin-exact connect_to_net labels
- Verified: 15 clean nets with no GND/3V3 contamination
- Nets: 3V3, CC1, CC2, CFG1, CFG2, EN, GATE, IO0, USB_DN, USB_DP,
VBUS, VBUS_SENSE, VDD_CH224, VOUT, GND
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2026-06-20 17:47:37 +03:00 |
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f2d64ccf04
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Fix schematic syntax & finalize ERC
- Fixed: double-empty-string bug () in power symbol Footprint properties
- Fixed: single-line 67KB file was unparseable by KiCad - properly pretty-printed to 4408 lines
- Added: 42 no-connect flags for unused pins (J1 SBU, ESP32 GPIOs, NC resistors)
- Added: PWR_FLAG and GND power symbols connected to nets
- Added: batch_connect wiring for passives (C1-C5, R1-R7)
- Snap-to-grid: 152 elements aligned to 1.27mm grid
- Board sync: 13 footprints added, 16 nets confirmed
- Custom CH224K symbol verified and committed
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2026-06-20 17:40:26 +03:00 |
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ef2514c332
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USB-C PD board with ESP32-S3
Complete initial design:
- CH224K PD sink controller (custom corrected symbol)
- USB-C receptacle (16-pin USB2.0)
- P-Channel MOSFET VBUS switch
- LD1117S33 3.3V LDO regulator (800mA)
- ESP32-S3-WROOM-1 module
- 15 nets: VBUS, VOUT, 3V3, GATE, CC1/CC2, USB_DP/USB_DN
- 5.1kΩ CC pull-down resistors
- CFG1/CFG2 for PD voltage selection
- Input/output decoupling capacitors
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2026-06-20 17:31:20 +03:00 |
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