Add R9 (0.47R ESR for LD1117 stability) + R10 (22R gate resistor) + optimize placement

This commit is contained in:
2026-06-21 09:10:57 +03:00
parent 8ed0b7bb28
commit 77333e4e71
3 changed files with 401 additions and 1118 deletions

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@@ -511,6 +511,44 @@
"via_diameter": 0.6, "via_diameter": 0.6,
"via_drill": 0.3, "via_drill": 0.3,
"wire_width": 6 "wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "POWER",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 0,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 2.5,
"tuning_profile": "",
"via_diameter": 1.0,
"via_drill": 0.5,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "RAIL",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 0,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.5,
"tuning_profile": "",
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
} }
], ],
"meta": { "meta": {

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