Add R9 (0.47R ESR for LD1117 stability) + R10 (22R gate resistor) + optimize placement
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@@ -511,6 +511,44 @@
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"via_diameter": 0.6,
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"via_drill": 0.3,
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"wire_width": 6
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},
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{
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"bus_width": 12,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "POWER",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 0,
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 2.5,
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"tuning_profile": "",
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"via_diameter": 1.0,
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"via_drill": 0.5,
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"wire_width": 6
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},
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{
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"bus_width": 12,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "RAIL",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 0,
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.5,
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"tuning_profile": "",
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"via_diameter": 0.8,
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"via_drill": 0.4,
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"wire_width": 6
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}
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],
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"meta": {
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