mixelpixx 7fa6c350f4 Merge pull request #252 from gcolonese/feat-set-footprint-type ...

Note: get_component_properties 'attributes' response changed from raw bitmask ints to {type: smd|through_hole|unspecified, exclude_from_pos_files, exclude_from_bom, not_in_schematic}. Cleaner shape for AI consumers; callers parsing the old integer keys must update.

2026-06-12 12:18:25 -04:00

..

board

fix(board-view): frame get_board_2d_view to the board, not the A4 sheet

2026-06-04 15:26:05 -05:00

__init__.py

chore: normalize all tracked files to LF line endings

2026-04-18 15:23:00 +01:00

board.py

chore: normalize all tracked files to LF line endings

2026-04-18 15:23:00 +01:00

component_schematic.py

fix: correct pin location calculation and symbol reference dedup in kicad-skip

2026-04-18 23:31:14 +01:00

component.py

feat: add set_footprint_type tool for placement attribute control

2026-06-12 11:07:45 -04:00

connection_schematic.py

feat: multi-sheet net connectivity + sexp-based parsing reliability

2026-04-20 15:59:22 -07:00

datasheet_manager.py

chore: enable strict mypy checks and fix pre-commit mypy hook

2026-04-05 23:50:54 +01:00

design_rules.py

fix(swig): detect and recover from BOARD proxy dehydration (#173)

2026-05-22 17:38:59 -04:00

dynamic_symbol_loader.py

fix: restore property-position regex for RefDes/Value placement

2026-05-26 19:59:29 +02:00

export.py

chore: normalize all tracked files to LF line endings

2026-04-18 15:23:00 +01:00

footprint.py

chore: enable strict mypy checks and fix pre-commit mypy hook

2026-04-05 23:50:54 +01:00

freerouting.py

feat(autoroute): add best-of-N support (attempts, targetNets, passSchedule) (#190)

2026-05-18 23:03:38 -04:00

jlcpcb_downloader.py

fix(jlcpcb): skip re-download when cache file already complete (#199, #204)

2026-05-30 09:29:22 -04:00

jlcpcb_parts.py

fix(jlcpcb): use platform user data dir for parts database (#167)

2026-05-18 14:40:13 -04:00

jlcpcb.py

chore: normalize all tracked files to LF line endings

2026-04-18 15:23:00 +01:00

jlcsearch.py

fix(jlcpcb): download prebuilt catalog instead of broken JLCSearch offset loop (#199)

2026-05-24 11:53:12 -04:00

library_schematic.py

chore: normalize all tracked files to LF line endings

2026-04-18 15:23:00 +01:00

library_symbol.py

fix(library): rebuild SymbolLibraryManager when cache is empty

2026-06-01 18:12:36 +05:00

library.py

fix: parse quoted KiCad library table URIs with spaces

2026-05-24 12:34:47 +02:00

pin_locator.py

feat: add mil unit support across position/coordinate commands (#162)

2026-05-22 17:29:34 -04:00

project.py

chore: normalize all tracked files to LF line endings

2026-04-18 15:23:00 +01:00

routing.py

fix(routing): persist create_netclass net classes to .kicad_pro (#185)

2026-06-04 13:04:47 -05:00

schematic_analysis.py

chore: normalize all tracked files to LF line endings

2026-04-18 15:23:00 +01:00

schematic_batch.py

feat(schematic): batch component authoring + connection tools

2026-06-03 17:49:04 -04:00

schematic_field_layout.py

feat(schematic): reposition and auto-place Ref/Value field labels

2026-06-03 17:45:17 -04:00

schematic_hierarchy.py

feat(schematic): hierarchical sheet insertion and subsheet scaffolding

2026-06-03 17:41:12 -04:00

schematic_snap.py

fix: change snap_to_grid default grid from 2.54mm to 1.27mm (50 mil)

2026-04-12 18:10:55 +01:00

schematic_text_utils.py

feat(schematic): reposition and auto-place Ref/Value field labels

2026-06-03 17:45:17 -04:00

schematic.py

chore: normalize schematic.py and apply black to create_schematic signature

2026-04-18 15:24:02 +01:00

svg_import.py

chore: enable strict mypy checks and fix pre-commit mypy hook

2026-04-05 23:50:54 +01:00

symbol_creator.py

style: sort Python imports with isort

2026-03-29 13:02:24 +01:00

symbol_pins.py

feat(schematic): add list_symbol_pins to read pins from symbol libraries

2026-06-02 14:36:22 -07:00

wire_connectivity.py

fix(wire_connectivity): pwr-flags must not bridge unrelated power rails (#177)

2026-05-18 13:53:34 -04:00

wire_dragger.py

fix(pin_world_xy): align rotation direction and mirror axis with eeschema

2026-05-03 22:30:17 +01:00

wire_manager.py

fix: align global and hierarchical labels vertically centered

2026-06-05 14:11:43 -03:00