# Via Size Guide for Power Traces

**Date:** 2025-12-28  
**For:** 1mm power trace carrying 512mA (3.3V)

---

## Quick Answer

**For a 1mm power trace:**
- **Recommended via diameter:** **0.8mm**
- **Drill size:** 0.4mm
- **Alternative:** 0.6mm via (minimum) or use 2× vias in parallel

---

## Current Requirements

- **3.3V power trace:** 1mm width
- **Current:** 512mA peak (ESP32 + LEDs)
- **Application:** Power distribution via

---

## Via Current Capacity

### IPC-2221 Standard (Plated Through-Hole Vias)

| Via Diameter | Drill Size | Current Capacity (1oz) | Notes |
|--------------|------------|------------------------|-------|
| 0.2mm (8mil) | 0.1mm | ~200mA | Too small for power |
| 0.3mm (12mil) | 0.15mm | ~300mA | Too small for power |
| 0.4mm (16mil) | 0.2mm | ~400mA | Minimum for 512mA |
| **0.5mm (20mil)** | **0.25mm** | **~500mA** | **Minimum acceptable** |
| **0.6mm (24mil)** | **0.3mm** | **~600mA** | **Good choice** |
| **0.8mm (31mil)** | **0.4mm** | **~800mA** | **Recommended** |
| 1.0mm (39mil) | 0.5mm | ~1000mA | Excellent, if space allows |

---

## Recommended Via Specifications

### Option 1: Single Large Via (Recommended)

```
Via diameter:  0.8mm (31mil)
Drill size:    0.4mm (16mil)
Annular ring:  0.2mm (8mil) minimum
Plating:       Standard (1oz copper)
Current:       ~800mA capacity (56% margin)
```

**Pros:**
- Single via, easy to place
- Good current capacity with margin
- Standard size, widely available

**Cons:**
- Slightly larger than minimum

### Option 2: Multiple Smaller Vias (Best Practice)

```
Via diameter:  0.6mm (24mil) × 2
Drill size:    0.3mm (12mil) each
Annular ring:  0.15mm (6mil) minimum
Total capacity: ~1200mA (2× 600mA)
```

**Pros:**
- Lower resistance (parallel connection)
- Better thermal performance
- Redundancy if one via fails
- Can use smaller individual vias

**Cons:**
- Requires more board space
- More complex routing

### Option 3: Minimum Size (Not Recommended)

```
Via diameter:  0.5mm (20mil)
Drill size:    0.25mm (10mil)
Current:       ~500mA capacity (just enough)
```

**Pros:**
- Smallest acceptable size
- Saves board space

**Cons:**
- No safety margin
- Higher resistance
- Not recommended for power

---

## Via Size vs Trace Width

### General Rule

**For power traces:**
- **Via diameter ≥ trace width** (preferred)
- **Via diameter ≥ 0.8× trace width** (minimum)

**For your 1mm trace:**
- **Minimum via:** 0.8mm diameter
- **Recommended via:** 0.8mm - 1.0mm diameter
- **Best practice:** 0.8mm via or 2× 0.6mm vias

### Why Via Should Match or Exceed Trace Width?

1. **Current continuity:** Via should handle same current as trace
2. **Resistance:** Larger via = lower resistance
3. **Thermal:** Better heat dissipation
4. **Reliability:** Less stress on via plating

---

## Manufacturing Considerations

### Standard Via Sizes

**Commonly available from PCB manufacturers:**

| Size | Availability | Cost |
|------|--------------|------|
| 0.2mm | Standard | Standard |
| 0.3mm | Standard | Standard |
| 0.5mm | Standard | Standard |
| 0.6mm | Standard | Standard |
| 0.8mm | Standard | Standard |
| 1.0mm | Standard | Standard |

**Note:** Most manufacturers support 0.2mm - 1.0mm via sizes without extra cost.

### Minimum Requirements

- **Minimum via diameter:** 0.2mm (most manufacturers)
- **Minimum drill size:** 0.1mm (laser drilling)
- **Minimum annular ring:** 0.1mm (manufacturing tolerance)

---

## KiCad Via Setup

### Setting Up Power Vias in KiCad

1. **Via Settings:**
   - Go to: `File → Board Setup → Design Rules → Sizes`
   - Set default via size:
     - **Diameter:** 0.8mm
     - **Drill:** 0.4mm

2. **Net Class Settings:**
   - Go to: `File → Board Setup → Design Rules → Net Classes`
   - For `Power_3V3` class:
     - **Via diameter:** 0.8mm
     - **Via drill:** 0.4mm

3. **Routing:**
   - When routing power traces, KiCad will use the via size from net class
   - You can also manually set via size when placing vias

### Creating Custom Via Sizes

1. **Via Properties:**
   - Right-click via → Properties
   - Set custom diameter and drill size
   - Save as template if needed

---

## Best Practices

### For Power Distribution

1. **Use multiple vias:**
   - 2-3 vias in parallel for main power rails
   - Reduces resistance and improves reliability

2. **Via placement:**
   - Place vias close to component pads
   - Use vias at layer transitions
   - Avoid vias in high-frequency signal paths

3. **Via spacing:**
   - Minimum spacing: 2× via diameter
   - For power: Can be closer if needed

4. **Thermal vias:**
   - Consider thermal vias for heat dissipation
   - Especially near power components (regulator, ESP32)

### Example: Power Via Configuration

```
Main 3.3V rail (1mm trace):
  ┌─────────────────┐
  │  1mm trace      │
  │      │          │
  │      ▼          │
  │   [0.8mm via]   │  ← Single via
  │      │          │
  │  1mm trace      │
  └─────────────────┘

Or better:

  ┌─────────────────┐
  │  1mm trace      │
  │      │          │
  │   [0.6mm] [0.6mm]│  ← Two vias in parallel
  │      │          │
  │  1mm trace      │
  └─────────────────┘
```

---

## Current Capacity Verification

### Single 0.8mm Via

- **Capacity:** ~800mA
- **Required:** 512mA
- **Margin:** 56% (excellent)

### Two 0.6mm Vias in Parallel

- **Capacity:** ~1200mA (2× 600mA)
- **Required:** 512mA
- **Margin:** 134% (excellent)
- **Resistance:** Half of single via

---

## Summary

### Recommended Via for 1mm Power Trace

| Parameter | Value | Notes |
|-----------|-------|-------|
| **Via diameter** | **0.8mm** | Recommended |
| **Drill size** | **0.4mm** | Standard |
| **Annular ring** | **0.2mm** | Minimum |
| **Current capacity** | **~800mA** | 56% margin |
| **Alternative** | **2× 0.6mm** | Best practice |

### Quick Reference

- **1mm trace → 0.8mm via** (recommended)
- **1mm trace → 2× 0.6mm vias** (best practice)
- **Minimum:** 0.5mm via (not recommended, no margin)

---

## Design Checklist

- [ ] Via diameter: **0.8mm** (or 2× 0.6mm)
- [ ] Drill size: **0.4mm** (for 0.8mm via)
- [ ] Annular ring: **0.2mm minimum**
- [ ] Multiple vias: Consider 2-3 vias for main power rails
- [ ] Via placement: Close to component pads
- [ ] Manufacturing: Verify with PCB manufacturer

---

*Guide created: 2025-12-28*

